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Travelled to:
1 × France
1 × Germany
2 × USA
Collaborated with:
P.S.Roop Z.Salcic S.Basu John Spray M.M.Y.Kuo S.Andalam A.Girault J.Reineke
Talks about:
analysi (2) design (2) multi (2) use (2) architectur (1) construct (1) synchron (1) reachabl (1) protocol (1) maintain (1)

Person: Roopak Sinha

DBLP DBLP: Sinha:Roopak

Contributed to:

DAC 20132013
DATE 20122012
DAC 20112011
DATE 20092009
ECSA 20182018

Wrote 5 papers:

DAC-2013-AndalamGSRR #analysis #precise
Precise timing analysis for direct-mapped caches (SA, AG, RS, PSR, JR), p. 10.
DATE-2012-SinhaRSB #component #design #multi
Correct-by-construction multi-component SoC design (RS, PSR, ZS, SB), pp. 647–652.
DAC-2011-KuoSR #analysis #performance #reachability #source code #using
Efficient WCRT analysis of synchronous programs using reachability (MMYK, RS, PSR), pp. 480–485.
DATE-2009-SinhaRBS #design #multi #protocol #using
Multi-clock Soc design using protocol conversion (RS, PSR, SB, ZS), pp. 123–128.
ECSA-2018-SprayS #abstraction #architecture #embedded
Abstraction Layered Architecture: Writing Maintainable Embedded Code (JS, RS), pp. 131–146.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.