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Travelled to:
1 × The Netherlands
2 × France
2 × Germany
2 × USA
Collaborated with:
R.Sinha S.Andalam A.Girault Z.Salcic S.Basu R.Malik M.M.Y.Kuo J.Reineke J.Aguado M.Mendler M.Pouzet R.v.Hanxleden
Talks about:
analysi (3) use (3) determinist (2) synchron (2) program (2) design (2) multi (2) clock (2) wcrt (2) multithread (1)

Person: Partha S. Roop

DBLP DBLP: Roop:Partha_S=

Contributed to:

DAC 20132013
DATE 20122012
DAC 20112011
DATE 20112011
DATE 20102010
DATE 20092009
IFM 20052005
ESOP 20182018

Wrote 8 papers:

DAC-2013-AndalamGSRR #analysis #precise
Precise timing analysis for direct-mapped caches (SA, AG, RS, PSR, JR), p. 10.
DATE-2012-SinhaRSB #component #design #multi
Correct-by-construction multi-component SoC design (RS, PSR, ZS, SB), pp. 647–652.
DAC-2011-KuoSR #analysis #performance #reachability #source code #using
Efficient WCRT analysis of synchronous programs using reachability (MMYK, RS, PSR), pp. 480–485.
DATE-2011-AndalamRG #analysis #source code
Pruning infeasible paths for tight WCRT analysis of synchronous programs (SA, PSR, AG), pp. 204–209.
DATE-2010-AndalamRG #multi #predict #thread #using
Deterministic, predictable and light-weight multithreading using PRET-C (SA, PSR, AG), pp. 1653–1656.
DATE-2009-SinhaRBS #design #multi #protocol #using
Multi-clock Soc design using protocol conversion (RS, PSR, SB, ZS), pp. 123–128.
IFM-2005-MalikR #adaptation #case study #comparative #embedded #specification
Adaptive Techniques for Specification Matching in Embedded Systems: A Comparative Study (RM, PSR), pp. 33–52.
ESOP-2018-AguadoMPRH #approach #concurrent #memory management
Deterministic Concurrency: A Clock-Synchronised Shared Memory Approach (JA, MM, MP, PSR, RvH), pp. 86–113.

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