1 × France
1 × Germany
1 × Sweden
3 × USA
L.Liu S.Yin P.Ouyang D.Liu Y.Guo G.Jiang W.Zhu C.Meng J.Wang J.Zhu F.Tu J.Li C.Chan D.Hanford J.Y.Pan N.V.Shenoy M.Mehendale A.Vasudevan
reconfigur (3) acceler (3) loop (3) architectur (2) featur (2) effici (2) optim (2) cgras (2) affin (2) nest (2)
Person: Shaojun Wei
Wrote 10 papers:
- DAC-2015-JiangLZYW #effectiveness #feature model #image #performance
- A 127 fps in full hd accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction (GJ, LL, WZ, SY, SW), p. 6.
- DAC-2015-MengYOLW #array #clustering #data access #memory management #parallel #performance
- Efficient memory partitioning for parallel data access in multidimensional arrays (CM, SY, PO, LL, SW), p. 6.
- DAC-2015-WangLZYW #architecture #configuration management #control flow
- Acceleration of control flows on reconfigurable architecture with a composite method (JW, LL, JZ, SY, SW), p. 6.
- DATE-2015-TuYOLW #architecture #configuration management #hardware #named
- RNA: a reconfigurable architecture for hardware neural acceleration (FT, SY, PO, LL, SW), pp. 695–700.
- DATE-2015-YinLLWG #pipes and filters
- Joint affine transformation and loop pipelining for mapping nested loop on CGRAs (SY, DL, LL, SW, YG), pp. 115–120.
- DATE-2015-YinLLWG15a #policy
- Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache (SY, JL, LL, SW, YG), pp. 187–192.
- DATE-2014-YinOLW #configuration management
- Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms (SY, PO, LL, SW), pp. 1–6.
- ICPR-2014-OuyangYLW #performance #robust
- A FAST Extreme Illumination Robust Feature in Affine Space (PO, SY, LL, SW), pp. 2365–2370.
- DAC-2013-LiuYLW #modelling #optimisation
- Polyhedral model based mapping optimization of loop nests for CGRAs (DL, SY, LL, SW), p. 8.
- DAC-2003-ChanHPSMVW #design
- Emerging markets: design goes global (CFC, DH, JYP, NVS, MM, AV, SW), p. 195.