Travelled to:1 × China
4 × USA
Collaborated with:S.J.Patel J.Gao W.W.Hwu N.C.Crago O.Azizi J.Gu R.Kumar Y.Sun F.Spadini B.Fahs H.Kim I.E.Hajj J.A.Stratton S.Ryoo S.Ueng J.H.Kelm I.Gelado S.S.Stone R.E.Kidd S.S.Baghsorkhi A.Mahesri S.C.Tsao N.Navarro M.I.Frank
Talks about:parallel (2) schedul (2) program (2) model (2) data (2) core (2) microprocessor (1) interprocess (1) architectur (1) processor (1)
Person: Steven S. Lumetta
DBLP: Lumetta:Steven_S=
Contributed to:
2015
20132011
20072003
2018Wrote 6 papers:
- CGO-2015-KimHSLH #architecture #concurrent #cpu #modelling #programming #scheduling #thread
- Locality-centric thread scheduling for bulk-synchronous programming models on CPU architectures (HSK, IEH, JAS, SSL, WmWH), pp. 257–268.
- HPCA-2013-CragoALP #energy #hybrid #latency #parallel #robust
- Hybrid latency tolerance for robust energy-efficiency on 1000-core data parallel processors (NCC, OA, SSL, SJP), pp. 294–305.
- HPCA-2011-GuLKS #named
- MOPED: Orchestrating interprocess message data on CMPs (JG, SSL, RK, YS), pp. 111–120.
- DAC-2007-HwuRUKGSKBMTNLFP #modelling #parallel #programming
- Implicitly Parallel Programming Models for Thousand-Core Microprocessors (WmWH, SR, SZU, JHK, IG, SSS, REK, SSB, AM, SCT, NN, SSL, MIF, SJP), pp. 754–759.
- CGO-2003-SpadiniFPL
- Improving Quasi-Dynamic Schedules through Region Slip (FS, BF, SJP, SSL), pp. 149–158.
- ASE-2018-GaoL #reduction
- Loop path reduction by state pruning (JG, SSL), pp. 838–843.