Travelled to:5 × USA
Collaborated with:T.Chiba K.Yoshida E.S.Kuh M.Takashima M.Murofushi T.Ishioka M.Murakata Y.Nakada K.Ogita S.Nakatsuka
Talks about:circuit (2) artwork (2) system (2) layout (2) integr (2) power (2) mask (2) synthesi (1) consumpt (1) topolog (1)
Person: Takashi Mitsuhashi
DBLP: Mitsuhashi:Takashi
Contributed to:
19971992198219801977Wrote 5 papers:
- DAC-1997-MurofushiIMM #layout #power management
- Layout Driven Re-synthesis for Low Power Consumption LSIs (MM, TI, MM, TM), pp. 666–669.
- DAC-1992-MitsuhashiK #network #optimisation
- Power and Ground Network Topology Optimization for Cell Based VLSIs (TM, ESK), pp. 524–529.
- DAC-1982-TakashimaMCY #source code #verification
- Programs for verifying circuit connectivity of mos/lsi mask artwork (MT, TM, TC, KY), pp. 544–550.
- DAC-1980-MitsuhashiCTY #analysis
- An integrated mask artwork analysis system (TM, TC, MT, KY), pp. 277–284.
- DAC-1977-YoshidaMNCON #layout #scalability
- A layout checking system for large scale integrated circuits (KY, TM, YN, TC, KO, SN), pp. 322–330.