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Travelled to:
5 × USA
Collaborated with:
T.Chiba K.Yoshida E.S.Kuh M.Takashima M.Murofushi T.Ishioka M.Murakata Y.Nakada K.Ogita S.Nakatsuka
Talks about:
circuit (2) artwork (2) system (2) layout (2) integr (2) power (2) mask (2) synthesi (1) consumpt (1) topolog (1)

Person: Takashi Mitsuhashi

DBLP DBLP: Mitsuhashi:Takashi

Contributed to:

DAC 19971997
DAC 19921992
DAC 19821982
DAC 19801980
DAC 19771977

Wrote 5 papers:

DAC-1997-MurofushiIMM #layout #power management
Layout Driven Re-synthesis for Low Power Consumption LSIs (MM, TI, MM, TM), pp. 666–669.
DAC-1992-MitsuhashiK #network #optimisation
Power and Ground Network Topology Optimization for Cell Based VLSIs (TM, ESK), pp. 524–529.
DAC-1982-TakashimaMCY #source code #verification
Programs for verifying circuit connectivity of mos/lsi mask artwork (MT, TM, TC, KY), pp. 544–550.
DAC-1980-MitsuhashiCTY #analysis
An integrated mask artwork analysis system (TM, TC, MT, KY), pp. 277–284.
DAC-1977-YoshidaMNCON #layout #scalability
A layout checking system for large scale integrated circuits (KY, TM, YN, TC, KO, SN), pp. 322–330.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.