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Travelled to:
1 × Germany
1 × USA
Collaborated with:
W.Luk S.Stilkerich Q.Liu
Talks about:
design (2) reconfigur (1) monitor (1) circuit (1) tempor (1) runtim (1) combin (1) verif (1) power (1) optim (1)

Person: Tim Todman

DBLP DBLP: Todman:Tim

Contributed to:

DAC 20152015
DATE 20102010

Wrote 2 papers:

DAC-2015-TodmanSL #configuration management #design #monitoring #runtime #verification
In-circuit temporal monitors for runtime verification of reconfigurable designs (TT, SS, WL), p. 6.
DATE-2010-LiuTL #automation #design #optimisation #power management
Combining optimizations in automated low power design (QL, TT, WL), pp. 1791–1796.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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