Travelled to:1 × Germany
3 × France
Collaborated with:H.Yasuura F.Fallah M.Sugihara K.Murakami H.Tomiyama A.Inoue
Talks about:processor (3) power (3) techniqu (2) schedul (2) system (2) specif (2) reduct (2) applic (2) cach (2) multiprocessor (1)
Person: Tohru Ishihara
DBLP: Ishihara:Tohru
Contributed to:
2007200520001998Wrote 4 papers:
- DATE-2007-SugiharaIM #architecture #multi #reliability #scheduling
- Task scheduling for reliable cache architectures of multiprocessor systems (MS, TI, KM), pp. 1490–1495.
- DATE-2005-IshiharaF #power management
- A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors (TI, FF), pp. 358–363.
- DATE-2000-IshiharaY #embedded #reduction
- A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors (TI, HY), pp. 617–623.
- DATE-1998-TomiyamaIIY #design #reduction #scheduling
- Instruction Scheduling for Power Reduction in Processor-Based System Design (HT, TI, AI, HY), pp. 855–860.