Travelled to:1 × France
2 × USA
Collaborated with:A.Nahir M.Dusanapudi S.Kapoor K.Reick K.Schubert K.Sharp G.Wetli H.Yagi T.Kogel E.Haritan H.Tangi M.McNamara G.Smith N.Dutt G.Mancini S.Bergman G.Bobok W.Kowalski S.Koyfman S.Moran Z.Nevo A.Orni V.Paruthi G.Shurek V.Vuyyuru
Talks about:processor (1) industri (1) silicon (1) fiction (1) experi (1) design (1) verif (1) valid (1) stori (1) power (1)
Person: Wolfgang Roesner
DBLP: Roesner:Wolfgang
Contributed to:
2015
20142008Wrote 3 papers:
- DATE-2015-BergmanBKKMNOPR #experience #industrial #verification
- Designer-level verification: an industrial experience story (SB, GB, WK, SK, SM, ZN, AO, VP, WR, GS, VV), pp. 410–411.
- DAC-2014-NahirDKRRSSW #validation
- Post-Silicon Validation of the IBM POWER8 Processor (AN, MD, SK, KR, WR, KDS, KS, GW), p. 6.
- DAC-2008-YagiRKHTMSDM #question
- ESL hand-off: fact or EDA fiction? (HY, WR, TK, EH, HT, MM, GS, ND, GM), pp. 310–312.