BibSLEIGH — Amir

Travelled to:

2 × France
2 × Germany
6 × USA

Collaborated with:

A.Ziv A.J.Hu F.M.d.Paula A.Adir V.Sokhin G.Shurek W.Kadry C.Meissner C.Eisner K.Yorav A.Morgenshtein J.Schumann S.Landa V.Bertacco S.Kapoor O.Friedler Z.Nevo A.Orni R.Emek T.Keidar N.Ronen B.Mammo D.Chatterjee D.Pidan R.Morad M.Golubev M.Dusanapudi K.Reick W.Roesner K.Schubert K.Sharp G.Wetli S.Copty D.Krestyashyn J.S.Park S.Park W.Jeong J.Son R.Galivanche M.Abramovici A.Camilleri B.Bentley H.Foster D.Goodman D.Hershcovich O.Hershkovitz B.G.Hickerson K.Holtz A.Koyfman J.M.Ludden R.R.Pratt M.Schiffli B.S.Onge B.W.Thompto E.Tsanko

Talks about:

silicon (10) post (7) verif (6) valid (4) power (4) processor (3) pre (3) generat (2) acceler (2) trace (2)

Person: Amir Nahir

DBLP: Nahir:Amir

Contributed to:

2015

2014

2012

2011

2010

2008

2006

Wrote 13 papers:

DATE-2015-KadryKMNSPPJS #case study #comparative #generative #simulation #testing: Comparative study of test generation methods for simulation accelerators (WK, DK, AM, AN, VS, JSP, SBP, WJ, JCS), pp. 321–324.
DAC-2014-AdirGHHHHKKLMNPSOTTZ #memory management #transaction #verification: Verification of Transactional Memory in POWER8 (AA, DG, DH, OH, BGH, KH, WK, AK, JML, CM, AN, RRP, MS, BSO, BWT, ET, AZ), p. 6.
DAC-2014-NahirDKRRSSW #validation: Post-Silicon Validation of the IBM POWER8 Processor (AN, MD, SK, KR, WR, KDS, KS, GW), p. 6.
DATE-2014-FriedlerKMNS #effectiveness #locality #slicing #using: Effective post-silicon failure localization using dynamic program slicing (OF, WK, AM, AN, VS), pp. 1–6.
CAV-2012-PaulaHN #debugging #named #nondeterminism: nuTAB-BackSpace: Rewriting to Normalize Non-determinism in Post-silicon Debug Traces (FMdP, AJH, AN), pp. 513–531.
DATE-2012-MammoCPNZMB #approximate #simulation: Approximating checkers for simulation acceleration (BM, DC, DP, AN, AZ, RM, VB), pp. 153–158.
DAC-2011-AdirGLNSSZ #concurrent #multi #named #thread: Threadmill: a post-silicon exerciser for multi-threaded processors (AA, MG, SL, AN, GS, VS, AZ), pp. 860–865.
DAC-2011-AdirNSZMS #validation #verification: Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor (AA, AN, GS, AZ, CM, JS), pp. 569–574.
DAC-2011-PaulaNNOH #named: TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead (FMdP, AN, ZN, AO, AJH), pp. 411–416.
DATE-2011-AdirCLNSZMS #validation #verification: A unified methodology for pre-silicon verification and post-silicon validation (AA, SC, SL, AN, GS, AZ, CM, JS), pp. 1590–1595.
DAC-2010-NahirZGHACBFBK #validation #verification: Bridging pre-silicon verification and post-silicon validation (AN, AZ, RG, AJH, MA, AC, BB, HF, VB, SK), pp. 94–95.
CAV-2008-EisnerNY #composition #design #functional #power management #reasoning #verification: Functional Verification of Power Gated Designs by Compositional Reasoning (CE, AN, KY), pp. 433–445.
DAC-2006-NahirZEKR #generative #multi #testing #verification: Scheduling-based test-case generation for verification of multimedia SoCs (AN, AZ, RE, TK, NR), pp. 348–351.