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Travelled to:
2 × France
4 × USA
Collaborated with:
O.Grumberg A.Adir A.Nahir A.Ziv C.Meissner J.Schumann S.Landa M.Golubev V.Sokhin S.Copty A.Aharon D.Goodman M.Levinger Y.Lichtenstein Y.Malka C.Metzger M.Molcho E.Bin A.Ghanayim K.Holtz E.Marcus R.Morad O.Peled M.Rimon E.Tsanko S.Bergman G.Bobok W.Kowalski S.Koyfman S.Moran Z.Nevo A.Orni V.Paruthi W.Roesner V.Vuyyuru
Talks about:
verif (6) silicon (5) processor (3) post (3) valid (2) power (2) pre (2) ibm (2) methodolog (1) threadmil (1)

Person: Gil Shurek

DBLP DBLP: Shurek:Gil

Contributed to:

DATE 20152015
DAC 20112011
DATE 20112011
SEKE 20102010
DAC 19951995
CAV 19901990

Wrote 7 papers:

DATE-2015-BergmanBKKMNOPR #experience #industrial #verification
Designer-level verification: an industrial experience story (SB, GB, WK, SK, SM, ZN, AO, VP, WR, GS, VV), pp. 410–411.
DAC-2011-AdirGLNSSZ #concurrent #multi #named #thread
Threadmill: a post-silicon exerciser for multi-threaded processors (AA, MG, SL, AN, GS, VS, AZ), pp. 860–865.
DAC-2011-AdirNSZMS #validation #verification
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor (AA, AN, GS, AZ, CM, JS), pp. 569–574.
DATE-2011-AdirCLNSZMS #validation #verification
A unified methodology for pre-silicon verification and post-silicon validation (AA, SC, SL, AN, GS, AZ, CM, JS), pp. 1590–1595.
SEKE-2010-BinGHMMPRST #hardware #ontology #tool support #verification
Ontology-Based Tools in the Service of Hardware Verification (EB, AG, KH, EM, RM, OP, MR, GS, ET), pp. 303–308.
DAC-1995-AharonGLLMMMS #functional #generative #verification
Test Program Generation for Functional Verification of PowerPC Processors in IBM (AA, DG, ML, YL, YM, CM, MM, GS), pp. 279–285.
CAV-1990-ShurekG #composition #framework #verification
The Modular Framework of Computer-Aided Verification (GS, OG), pp. 214–223.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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