BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × Brazil
1 × France
1 × Italy
1 × Korea
1 × Sweden
1 × Switzerland
2 × Germany
2 × USA
Collaborated with:
D.Tong X.Guan S.S.Somé T.Huang Q.Zhong K.Wang K.Wang L.Duan M.Xie K.Huang N.Li H.Guo Z.Wu M.Tie H.Dong T.Wang S.Liu Y.Feng Z.Zhou N.Qu Y.Zhao M.Tan X.Liu Z.Xie X.Wang
Talks about:
system (5) level (3) clock (3) approach (2) schedul (2) partit (2) memori (2) energi (2) effici (2) reduc (2)

Person: Xu Cheng


Contributed to:

HPCA 20142014
ICPR 20142014
DATE 20122012
SAC 20122012
DATE 20102010
SAC 20102010
SAC 20082008
DATE 20072007
SAC 20072007
DAC 20062006

Wrote 11 papers:

HPCA-2014-XieTHC #clustering #memory management #throughput
Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning (MX, DT, KH, XC), pp. 344–355.
ICPR-2014-LiCGW #hybrid #interactive #recognition #using
A Hybrid Method for Human Interaction Recognition Using Spatio-temporal Interest Points (NL, XC, HG, ZW), pp. 2513–2518.
DATE-2012-TanLXTC #branch #energy #predict #stack
Energy-efficient branch prediction with Compiler-guided History Stack (MT, XL, ZX, DT, XC), pp. 449–454.
SAC-2012-HuangZGWCW #clustering
Reducing last level cache pollution through OS-level software-controlled region-based partitioning (TH, QZ, XG, XW, XC, KW), pp. 1779–1784.
SAC-2012-ZhongGHCW #memory management
Affinity-aware DMA buffer management for reducing off-chip memory access (QZ, XG, TH, XC, KW), pp. 1588–1593.
DATE-2010-TieDWC #performance #reduction #scheduling
Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement (MT, HD, TW, XC), pp. 520–525.
SAC-2010-LiuCGT #energy #mobile #performance
Energy efficient management scheme for heterogeneous secondary storage system in mobile computers (SL, XC, XG, DT), pp. 251–257.
SAC-2008-SomeC #approach #case study #generative
An approach for supporting system-level test scenarios generation from textual use cases (SSS, XC), pp. 724–729.
DATE-2007-FengZTC #design #fault #metric #validation
Clock domain crossing fault model and coverage metric for validation of SoC design (YF, ZZ, DT, XC), pp. 1385–1390.
SAC-2007-QuZGC #framework #named #platform
Unichos: a full system simulator for thin client platform (NQ, YZ, XG, XC), pp. 1552–1556.
DAC-2006-WangDC #approach #named #scheduling #tool support
ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling (KW, LD, XC), pp. 951–954.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.