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Travelled to:
1 × Germany
1 × USA
Collaborated with:
L.Fournier M.Levinger A.Adir B.Dubrov Y.Lichtenstein M.Rimon M.Vinov M.A.Calligaro A.Cofler G.Duffy
Talks about:
microprocessor (2) verif (2) methodolog (1) parallel (1) function (1) program (1) generat (1) genesi (1) famili (1) applic (1)

Person: Yaron Arbetman

DBLP DBLP: Arbetman:Yaron

Contributed to:

DAC 20052005
DATE 19991999

Wrote 2 papers:

DAC-2005-AdirADLRVCCD #case study #named #parallel #verification
VLIW: a case study of parallelism verification (AA, YA, BD, YL, MR, MV, MAC, AC, GD), pp. 779–782.
DATE-1999-FournierAL #functional #product line #using #verification
Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family (LF, YA, ML), pp. 434–441.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.