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Travelled to:
1 × Germany
2 × USA
Collaborated with:
M.Levinger A.Koyfman Y.Arbetman A.Adir S.Asaf I.Jaeger O.Peled
Talks about:
architectur (3) microprocessor (2) valid (2) applicaiton (1) methodolog (1) processor (1) framework (1) complianc (1) function (1) program (1)

Person: Laurent Fournier

DBLP DBLP: Fournier:Laurent

Contributed to:

DAC 20072007
DAC 19991999
DATE 19991999

Wrote 3 papers:

DAC-2007-AdirAFJP #architecture #framework #validation
A Framework for the Validation of Processor Architecture Compliance (AA, SA, LF, IJ, OP), pp. 902–905.
DAC-1999-FournierKL #architecture #validation
Developing an Architecture Validation Suite: Applicaiton to the PowerPC Architecture (LF, AK, ML), pp. 189–194.
DATE-1999-FournierAL #functional #product line #using #verification
Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family (LF, YA, ML), pp. 434–441.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.