Person: Allon Adir

DBLP: Adir:Allon

Contributed to:

2014

2011

2011

2007

2005

Wrote 8 papers:

DAC-2014-AdirGGS #generative #network #testing #using

Using a High-Level Test Generation Expert System for Testing In-Car Networks (AA, AG, LG, TS), p. 6.

DAC-2014-AdirGHHHHKKLMNPSOTTZ #memory management #transaction #verification

Verification of Transactional Memory in POWER8 (AA, DG, DH, OH, BGH, KH, WK, AK, JML, CM, AN, RRP, MS, BSO, BWT, ET, AZ), p. 6.

DAC-2011-AdirGLNSSZ #concurrent #multi #named #thread

Threadmill: a post-silicon exerciser for multi-threaded processors (AA, MG, SL, AN, GS, VS, AZ), pp. 860–865.

DAC-2011-AdirNSZMS #validation #verification

Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor (AA, AN, GS, AZ, CM, JS), pp. 569–574.

DATE-2011-AdirCLNSZMS #validation #verification

A unified methodology for pre-silicon verification and post-silicon validation (AA, SC, SL, AN, GS, AZ, CM, JS), pp. 1590–1595.

DAC-2007-AdirAFJP #architecture #framework #validation

A Framework for the Validation of Processor Architecture Compliance (AA, SA, LF, IJ, OP), pp. 902–905.

DAC-2005-AdirABPS #approach #architecture #testing #verification

A generic micro-architectural test plan approach for microprocessor verification (AA, HA, EB, OP, KS), pp. 769–774.

DAC-2005-AdirADLRVCCD #case study #named #parallel #verification

VLIW: a case study of parallelism verification (AA, YA, BD, YL, MR, MV, MAC, AC, GD), pp. 779–782.