BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × France
4 × USA
Collaborated with:
A.Nahir A.Ziv G.Shurek O.Peled C.Meissner J.Schumann S.Landa A.Goryachev L.Greenberg T.Salman S.Asaf L.Fournier I.Jaeger H.Azatchi E.Bin K.Shoikhet M.Golubev V.Sokhin S.Copty Y.Arbetman B.Dubrov Y.Lichtenstein M.Rimon M.Vinov M.A.Calligaro A.Cofler G.Duffy D.Goodman D.Hershcovich O.Hershkovitz B.G.Hickerson K.Holtz W.Kadry A.Koyfman J.M.Ludden R.R.Pratt M.Schiffli B.S.Onge B.W.Thompto E.Tsanko
Talks about:
silicon (5) verif (5) processor (3) valid (3) test (3) post (3) architectur (2) power (2) pre (2) microprocessor (1)

Person: Allon Adir

DBLP DBLP: Adir:Allon

Contributed to:

DAC 20142014
DAC 20112011
DATE 20112011
DAC 20072007
DAC 20052005

Wrote 8 papers:

DAC-2014-AdirGGS #generative #network #testing #using
Using a High-Level Test Generation Expert System for Testing In-Car Networks (AA, AG, LG, TS), p. 6.
DAC-2014-AdirGHHHHKKLMNPSOTTZ #memory management #transaction #verification
Verification of Transactional Memory in POWER8 (AA, DG, DH, OH, BGH, KH, WK, AK, JML, CM, AN, RRP, MS, BSO, BWT, ET, AZ), p. 6.
DAC-2011-AdirGLNSSZ #concurrent #multi #named #thread
Threadmill: a post-silicon exerciser for multi-threaded processors (AA, MG, SL, AN, GS, VS, AZ), pp. 860–865.
DAC-2011-AdirNSZMS #validation #verification
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor (AA, AN, GS, AZ, CM, JS), pp. 569–574.
DATE-2011-AdirCLNSZMS #validation #verification
A unified methodology for pre-silicon verification and post-silicon validation (AA, SC, SL, AN, GS, AZ, CM, JS), pp. 1590–1595.
DAC-2007-AdirAFJP #architecture #framework #validation
A Framework for the Validation of Processor Architecture Compliance (AA, SA, LF, IJ, OP), pp. 902–905.
DAC-2005-AdirABPS #approach #architecture #testing #verification
A generic micro-architectural test plan approach for microprocessor verification (AA, HA, EB, OP, KS), pp. 769–774.
DAC-2005-AdirADLRVCCD #case study #named #parallel #verification
VLIW: a case study of parallelism verification (AA, YA, BD, YL, MR, MV, MAC, AC, GD), pp. 779–782.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.