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Travelled to:
1 × Germany
2 × USA
Collaborated with:
L.Fournier A.Koyfman Y.Arbetman A.Aharon D.Goodman Y.Lichtenstein Y.Malka C.Metzger M.Molcho G.Shurek
Talks about:
microprocessor (2) architectur (2) function (2) program (2) generat (2) verif (2) power (2) test (2) applicaiton (1) methodolog (1)

Person: Moshe Levinger

DBLP DBLP: Levinger:Moshe

Contributed to:

DAC 19991999
DATE 19991999
DAC 19951995

Wrote 3 papers:

DAC-1999-FournierKL #architecture #validation
Developing an Architecture Validation Suite: Applicaiton to the PowerPC Architecture (LF, AK, ML), pp. 189–194.
DATE-1999-FournierAL #functional #product line #using #verification
Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family (LF, YA, ML), pp. 434–441.
DAC-1995-AharonGLLMMMS #functional #generative #verification
Test Program Generation for Functional Verification of PowerPC Processors in IBM (AA, DG, ML, YL, YM, CM, MM, GS), pp. 279–285.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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