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Travelled to:
1 × France
1 × USA
Collaborated with:
B.Raghunathan S.Garg D.Marculescu G.Bejerano W.J.Dally
Talks about:
processor (3) multi (2) chip (2) architectur (1) synthesi (1) eterogen (1) silicon (1) process (1) homogen (1) exploit (1)

Person: Yatish Turakhia

DBLP DBLP: Turakhia:Yatish

Contributed to:

DAC 20132013
DATE 20132013
ASPLOS 20182018

Wrote 3 papers:

DAC-2013-TurakhiaRGM #architecture #multi #named #synthesis
HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors (YT, BR, SG, DM), p. 7.
DATE-2013-RaghunathanTGM #multi #named #process
Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors (BR, YT, SG, DM), pp. 39–44.
ASPLOS-2018-TurakhiaBD #assembly #named
Darwin: A Genomics Co-processor Provides up to 15, 000X Acceleration on Long Read Assembly (YT, GB, WJD), pp. 199–213.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.