BibSLEIGH — Diana

Travelled to:

14 × USA
6 × Germany
7 × France

Collaborated with:

R.Marculescu S.Garg M.Pedram N.Miskov-Zivanov K.Wu S.Herbert P.Stanley-Marbell Ü.Y.Ogras D.Juan Z.Chen Y.Turakhia B.Raghunathan S.R.Nassif E.Talpes ∅ V.S.P.Rapaka A.Iyer C.Tsui J.R.Faeder P.K.Khosla M.Shafique J.Henkel Y.Chuang Y.Chang M.Lee S.Chang P.Choudhary S.Haga N.Reeves R.Barua Z.Qian P.Bogdan K.Duraisamy R.G.Kim W.Choi G.Liu P.P.Pande M.Lindwer T.Basten R.Zimmermann S.Jung E.Cantatore

Talks about:

power (10) analysi (9) variat (7) chip (7) system (6) model (6) level (6) variabl (5) design (5) frequenc (4)

Person: Diana Marculescu

DBLP: Marculescu:Diana

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

1998

1997

1996

1995

Wrote 39 papers:

DAC-2015-DuraisamyKCLPMM #energy #manycore #performance #pipes and filters #platform: Energy efficient MapReduce with VFI-enabled multicore platforms (KD, RGK, WC, GL, PPP, RM, DM), p. 6.
DATE-2015-ChenM #distributed #learning #manycore #optimisation #performance: Distributed reinforcement learning for power limited many-core system performance optimization (ZC, DM), pp. 1521–1526.
DAC-2014-ShafiqueGHM #challenge #reliability #variability: The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives (MS, SG, JH, DM), p. 6.
DAC-2013-Miskov-ZivanovMF #analysis #automation #behaviour #design #network: Dynamic behavior of cell signaling networks: model design and analysis automation (NMZ, DM, JRF), p. 6.
DAC-2013-TurakhiaRGM #architecture #multi #named #synthesis: HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors (YT, BR, SG, DM), p. 7.
DATE-2013-QianJBTMM #analysis #named #performance #using: SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model (ZQ, DCJ, PB, CYT, DM, RM), pp. 354–357.
DATE-2013-RaghunathanTGM #multi #named #process: Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors (BR, YT, SG, DM), pp. 39–44.
DATE-2012-JuanCMC #modelling #optimisation #power management #statistics: Statistical thermal modeling and optimization considering leakage power variations (DCJ, YLC, DM, YWC), pp. 605–610.
DATE-2012-WuLMC #approach #correlation: Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms (KCW, MCL, DM, SCC), pp. 1269–1274.
DATE-2011-JuanGM #3d #evaluation #multi #process #statistics: Statistical thermal evaluation and mitigation techniques for 3D Chip-Multiprocessors in the presence of process variations (DCJ, SG, DM), pp. 383–388.
DATE-2011-WuM #analysis #optimisation: Aging-aware timing analysis and optimization considering path sensitization (KCW, DM), pp. 1572–1577.
DAC-2010-Miskov-ZivanovM #analysis #formal method #modelling #reasoning #reliability: Formal modeling and reasoning for reliability analysis (NMZ, DM), pp. 531–536.
DATE-2010-WuM #scheduling: Clock skew scheduling for soft-error-tolerant sequential circuits (KCW, DM), pp. 717–722.
DAC-2009-GargMMO #design #multi #perspective: Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective (SG, DM, RM, ÜYO), pp. 818–821.
DATE-2009-GargM #3d #analysis #process #variability: System-level process variability analysis and mitigation for 3D MPSoCs (SG, DM), pp. 604–609.
DATE-2009-WuM #logic #order #performance: Joint logic restructuring and pin reordering against NBTI-induced performance degradation (KCW, DM), pp. 75–80.
HPCA-2009-HerbertM #scalability: Variation-aware dynamic voltage/frequency scaling (SH, DM), pp. 301–312.
DAC-2008-HerbertM #multi #variability: Characterizing chip-multiprocessor variability-tolerance (SH, DM), pp. 313–318.
DAC-2008-OgrasMM #adaptation #feedback #multi: Variation-adaptive feedback control for networks-on-chip with multiple clock domains (ÜYO, RM, DM), pp. 614–619.
DATE-2008-MarculescuN #architecture #challenge #design #variability: Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level (DM, SRN).
DAC-2007-OgrasMCM #clustering: Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip (ÜYO, RM, PC, DM), pp. 110–115.
DATE-2007-GargM #analysis #design #interactive #multi #process #throughput: Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs (SG, DM), pp. 403–408.
DATE-2007-Miskov-ZivanovM #analysis #fault: Soft error rate analysis for sequential circuits (NMZ, DM), pp. 1436–1441.
DATE-2007-Stanley-MarbellM #communication #energy #interface #multi #power management: An 0.9 × 1.2”, low power, energy-harvesting system with custom multi-channel communication interface (PSM, DM), pp. 15–20.
DAC-2006-Miskov-ZivanovM #fault #modelling #named #reduction: MARS-C: modeling and reduction of soft errors in combinational circuits (NMZ, DM), pp. 767–772.
DAC-2005-MarculescuT #architecture #energy #perspective #variability: Variability and energy awareness: a microarchitecture-level perspective (DM, ET), pp. 11–16.
DATE-2005-Marculescu #bound #design #energy #fault tolerance: Energy Bounds for Fault-Tolerant Nanoscale Designs (DM), pp. 74–79.
DATE-v2-2004-Stanley-MarbellM #adaptation #fault tolerance: Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance (PSM, DM), pp. 968–973.
DATE-2003-HagaRBM #functional #power management: Dynamic Functional Unit Assignment for Low Power (SH, NR, RB, DM), pp. 11052–11057.
DATE-2003-LindwerMBZMJC #concept: Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts (ML, DM, TB, RZ, RM, SJ, EC), pp. 10010–10017.
DATE-2003-RapakaM #analysis #embedded #performance: Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and General Purpose Software Applications (VSPR, DM), pp. 10504–10509.
DAC-2002-MarculescuMK #challenge #modelling #optimisation: Challenges and opportunities in electronic textiles modeling and optimization (DM, RM, PKK), pp. 175–180.
DATE-2001-IyerM #architecture #power management #scalability: Power aware microarchitecture resource scaling (AI, DM), pp. 190–196.
DATE-1998-MarculescuMP #estimation #probability: Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation (DM, RM, MP), pp. 774–779.
DAC-1997-MarculescuMP #analysis #finite #probability #sequence #state machine: Sequence Compaction for Probabilistic Analysis of Finite-State Machines (DM, RM, MP), pp. 12–15.
DAC-1997-MarculescuMP97a #estimation #sequence: Hierarchical Sequence Compaction for Power Estimation (RM, DM, MP), pp. 570–575.
DAC-1996-MarculescuMP #generative #probability #sequence #synthesis: Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation (DM, RM, MP), pp. 696–701.
DAC-1996-TsuiMMP #performance: Improving the Efficiency of Power Simulators by Input Vector Compaction (CYT, RM, DM, MP), pp. 165–168.
DAC-1995-MarculescuMP #correlation #estimation #performance: Efficient Power Estimation for Highly Correlated Input Streams (RM, DM, MP), pp. 628–634.