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Travelled to:
2 × France
2 × USA
Collaborated with:
R.R.Chen T.Kawamoto C.Zhuang K.Sakanushi L.Jin T.Tsai R.Lee C.Chin C.Kuan H.Chen
Talks about:
layout (2) rout (2) parenthesi (1) boundari (1) sequenc (1) problem (1) polycel (1) minimum (1) channel (1) augment (1)

Person: Yoji Kajitani

DBLP DBLP: Kajitani:Yoji

Contributed to:

DATE 20112011
DATE 20022002
DAC 19841984
DAC 19791979

Wrote 4 papers:

DATE-2011-TsaiLCKCK #bound #on the
On routing fixed escaped boundary pins for high speed boards (TYT, RJL, CYC, CYK, HMC, YK), pp. 461–466.
DATE-2002-ZhuangKSJ
An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees (CZ, YK, KS, LJ), pp. 61–68.
DAC-1984-ChenK #design #layout #problem
The channel expansion problem in layout design (RRC, YK), pp. 388–391.
DAC-1979-KawamotoK
The minimum width routing of A 2-row 2-layer polycell-layout (TK, YK), pp. 290–296.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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