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Travelled to:
3 × France
3 × Germany
Collaborated with:
Y.Shi S.S.Liu C.Lee S.Chen R.Luo P.Pan C.Lin S.Liu L.Huang D.F.Wong Y.Chen T.Tsai C.Lu C.J.Liu W.Shih H.Hsu M.Chen H.Li C.Huang C.Lin C.Lee T.Tsai R.Lee C.Chin C.Kuan Y.Kajitani
Talks about:
effect (3) power (3) base (3) network (2) packag (2) design (2) rout (2) flip (2) chip (2) uncertainti (1)

Person: Hung-Ming Chen

DBLP DBLP: Chen:Hung=Ming

Contributed to:

DATE 20142014
DATE 20132013
DATE 20122012
DATE 20112011
DATE 20092009
DATE 20032003

Wrote 10 papers:

DATE-2014-ChenTCC #effectiveness
Cost-effective decap selection for beyond die power integrity (YEC, THT, SHC, HMC), pp. 1–4.
DATE-2014-ShiC #named
Memcomputing: The cape of good hope: [Extended special session description] (YS, HMC), pp. 1–3.
DATE-2013-LiuLC #algorithm
A network-flow based algorithm for power density mitigation at post-placement stage (SYSL, RGL, HMC), pp. 1707–1710.
DATE-2013-LiuLHCLL #clustering #effectiveness #linear #network #programming #prototype #statistics
Effective power network prototyping via statistical-based clustering and sequential linear programming (SYSL, CJL, CCH, HMC, CTL, CHL), pp. 1701–1706.
DATE-2013-PanCL #agile #design #named #parallel #performance #search-based #towards
PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design (PCP, HMC, CCL), pp. 1849–1854.
DATE-2012-HsuCCLC #effectiveness #on the #pseudo
On effective flip-chip routing via pseudo single redistribution layer (HWH, MLC, HMC, HCL, SHC), pp. 1597–1602.
DATE-2012-LiuLC #optimisation
Agglomerative-based flip-flop merging with signal wirelength optimization (SYL, CJL, HMC), pp. 1391–1396.
DATE-2011-TsaiLCKCK #bound #on the
On routing fixed escaped boundary pins for high speed boards (TYT, RJL, CYC, CYK, HMC, YK), pp. 461–466.
DATE-2009-LuCLS #co-evolution #design
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design (CHL, HMC, CNJL, WYS), pp. 845–850.
DATE-2003-HuangCW #nondeterminism
Global Wire Bus Configuration with Minimum Delay Uncertainty (LDH, HMC, DFW), pp. 10050–10055.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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