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platform (16)
system (13)
design (12)
applic (11)
memori (10)

Stem mpsoc$ (all stems)

55 papers:

DATEDATE-2015-ChenYQFM #evaluation #model checking #scheduling #statistics #using
Variation-aware evaluation of MPSoC task allocation and scheduling strategies using statistical model checking (MC, DY, XQ, XF, PM), pp. 199–204.
DATEDATE-2015-DuqueDY #adaptation #behaviour #fault #reliability #runtime
Improving MPSoC reliability through adapting runtime task schedule based on time-correlated fault behavior (LARD, JMMD, CY), pp. 818–823.
DATEDATE-2015-SarmaDGVN #paradigm #self
Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation (SS, NDD, PG, NV, AN), pp. 625–628.
DATEDATE-2015-SkalickySLF #framework #hardware #runtime
A unified hardware/software MPSoC system construction and run-time framework (SS, AGS, SL, MF), pp. 301–304.
DATEDATE-2014-LagraaTP #data mining #mining #scalability #simulation #using
Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces (SL, AT, FP), pp. 1–6.
DATEDATE-2014-LoiB #multi
A multi banked — Multi ported — Non blocking shared L2 cache for MPSoC platforms (IL, LB), pp. 1–6.
DATEDATE-2014-RobinoO
From Simulink to NoC-based MPSoC on FPGA (FR, ), pp. 1–4.
DATEDATE-2014-SarmaD #estimation #network #runtime
Minimal sparse observability of complex networks: Application to MPSoC sensor placement and run-time thermal estimation & tracking (SS, ND), pp. 1–6.
DATEDATE-2013-GangadharanCZ #scheduling
Quality-aware media scheduling on MPSoC platforms (DG, SC, RZ), pp. 976–981.
DATEDATE-2013-LagraaTP #concurrent #data access #data mining #identification #memory management #mining #simulation
Data mining MPSoC simulation traces to identify concurrent memory access patterns (SL, AT, FP), pp. 755–760.
DATEDATE-2013-SchonwaldVBR #deployment #memory management
Shared memory aware MPSoC software deployment (TS, AV, OB, WR), pp. 1771–1776.
DACDAC-2012-JeongESP #cpu #gpu #memory management
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC (MKJ, ME, CS, NCP), pp. 850–855.
DACDAC-2012-LearyCC #architecture #memory management #synthesis
System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC (GL, WC, KSC), pp. 672–677.
DACDAC-2012-MurilloEJYLA #hybrid #simulation
Synchronization for hybrid MPSoC full-system simulation (LGM, JFE, JJ, SY, RL, GA), pp. 121–126.
DATEDATE-2011-FourmigueBNAO #3d #architecture #evaluation #multi
Multi-granularity thermal evaluation of 3D MPSoC architectures (AF, GB, GN, EMA, IO), pp. 575–578.
DATEDATE-2011-KunzGW #hardware #memory management #performance #transaction
Improving the efficiency of a hardware transactional memory on an NoC-based MPSoC (LK, GG, FRW), pp. 1168–1171.
DATEDATE-2011-YehHWL #framework #simulation
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method (YFY, CYH, CAW, HCL), pp. 353–358.
DACDAC-2010-IosifidisMMGBSC #automation #framework #memory management #optimisation #parallel
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms (YI, AM, SM, EdG, AB, DS, FC), pp. 549–554.
DATEDATE-2010-CastrillonVSSCLAM #analysis
Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms (JC, RV, AS, WS, JC, RL, GA, HM), pp. 753–758.
DATEDATE-2010-JalierLJSBT #mobile
Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem (CJ, DL, AAJ, GS, PB, LT), pp. 184–189.
DATEDATE-2010-LeupersTNKWI #programming
Cool MPSoC programming (RL, LT, XN, BK, MW, TI), pp. 1488–1493.
DATEDATE-2010-MelloMGP #parallel #simulation
Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations (AM, IM, AG, FP), pp. 606–609.
LCTESLCTES-2010-ViskicLG #automation #design #framework #generative #network #process
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications (IV, LY, DG), pp. 77–84.
DATEDATE-2009-BaertBWA #using
Exploring parallelizations of applications for MPSoC platforms using MPA (RB, EB, SW, TJA), pp. 1148–1153.
DATEDATE-2009-DensmoreSDPS #design #evaluation #framework #using
UMTS MPSoC design evaluation using a system level design framework (DD, AS, AD, RP, ALSV), pp. 478–483.
DATEDATE-2009-HuangYX #scheduling
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms (LH, FY, QX), pp. 51–56.
DATEDATE-2009-JooKH #architecture #communication
On-chip communication architecture exploration for processor-pool-based MPSoC (YPJ, SK, SH), pp. 466–471.
DATEDATE-2009-LeupersVBHDN #exclamation #programming
Programming MPSoC platforms: Road works ahead! (RL, AV, MB, SH, RD, AN), pp. 1584–1589.
DATEDATE-2009-YangH #parallel #pipes and filters #scheduling
Pipelined data parallel task mapping/scheduling technique for MPSoC (HY, SH), pp. 69–74.
DATEDATE-2009-YangO #adaptation #towards
Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude (CY, AO), pp. 63–68.
DACDAC-2008-CengCSSLAMIK #framework #named #parallel
MAPS: an integrated framework for MPSoC application parallelization (JC, JC, WS, HS, RL, GA, HM, TI, HK), pp. 754–759.
DATEDATE-2008-BriaoBW #realtime
Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications (EWB, DB, FRW), pp. 1386–1389.
DATEDATE-2008-GerinGP #implementation #performance #simulation
Efficient Implementation of Native Software Simulation for MPSoC (PG, XG, FP), pp. 676–681.
DATEDATE-2008-HolzenspiesHKS #multi #runtime #streaming
Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC) (PKFH, JH, JK, GJMS), pp. 212–217.
DATEDATE-2008-LeupersAVAV #architecture #design #multi
System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures (RL, GA, WV, TA, AV).
ICLPICLP-2008-BeniniBM #constraints #multi #policy #programming #resource management #using
Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming (LB, DB, MM), pp. 470–484.
DACDAC-2007-ChandraiahD #flexibility #generative #parallel #specification
Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification (PC, RD), pp. 787–790.
DACDAC-2007-HuangHPBGLyCCJ #case study #design
Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264 (KH, SIH, KP, LBdB, XG, LL, XY, SIC, LC, AAJ), pp. 39–42.
DATEDATE-2007-BriereGBNMGO #assessment #framework
System level assessment of an optical NoC in an MPSoC platform (MB, BG, YB, GN, FM, FG, IO), pp. 1084–1089.
DATEDATE-2007-MedardoniRBBSP #communication #in memory #industrial #interactive #memory management
Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms (SM, MR, DB, LB, GS, CP), pp. 660–665.
DATEDATE-2007-SauerGD #composition #framework #interactive
Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform (CS, MG, SD), pp. 1102–1107.
LCTESLCTES-2007-ViskicAG #automation #communication #embedded #generative
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms (IV, SA, DDG), pp. 143–145.
DACDAC-2006-FlakeDS #design #tool support
System-level exploration tools for MPSoC designs (PF, SJD, FS), pp. 286–287.
DACDAC-2006-Martin #bibliography #challenge #design
Overview of the MPSoC design challenge (GM), pp. 274–279.
DATEDATE-2006-AngioliniCLFFB #design #framework
An integrated open framework for heterogeneous MPSoC design space exploration (FA, JC, RL, FF, CF, LB), pp. 1145–1150.
DATEDATE-2006-KlingaufGG #architecture #named #transaction
TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC (WK, HG, RG), pp. 1318–1323.
DATEDATE-2006-PasrichaD #architecture #communication #memory management #named
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC (SP, NDD), pp. 700–705.
DATEDATE-2006-ReyesKBAN #case study #design #modelling #simulation
A unified system-level modeling and simulation environment for MPSoC design: MPEG-4 decoder case study (VR, WK, TB, GA, AN), pp. 474–479.
DATEDATE-2006-X #architecture #design #tool support
4G applications, architectures, design methodology and tools for MPSoC, pp. 830–831.
DATEDATE-2006-XueOLKK #architecture #clustering #embedded #memory management
Dynamic partitioning of processing and memory resources in embedded MPSoC architectures (LX, ÖÖ, FL, MTK, IK), pp. 690–695.
DATEDATE-DF-2006-DumitrascuBPBJ #flexibility #framework #performance
Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application (FD, IB, LP, MB, AAJ), pp. 166–171.
DACDAC-2005-LiK #architecture
Locality-conscious workload assignment for array-based computations in MPSOC architectures (FL, MTK), pp. 95–100.
DACDAC-2004-YoussefYSPJ #case study #debugging #design #interface #video
Debugging HW/SW interface for MPSoC: video encoder system design case study (MWY, SY, AS, YP, AAJ), pp. 908–913.
DATEDATE-v2-2004-LoghiABBZ #communication
Analyzing On-Chip Communication in a MPSoC Environment (ML, FA, DB, LB, RZ), pp. 752–757.
DATEDATE-2003-YeBM #analysis #communication
Packetized On-Chip Interconnect Communication Analysis for MPSoC (TTY, LB, GDM), pp. 10344–10349.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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