Stem risc$ (all stems)

34 papers:

HPCA-2013-BlemMS #architecture

Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures (ERB, JM, KS), pp. 1–12.

DATE-2010-GoorGH #memory management #testing

Memory testing with a RISC microcontroller (AJvdG, GG, SH), pp. 214–219.

VLDB-2008-NeumannW #named #rdf

RDF-3X: a RISC-style engine for RDF (TN, GW), pp. 647–659.

SAC-2004-PanagopoulosPP #attribute grammar #evaluation #hardware

A hardware extension of the RISC microprocessor for Attribute Grammar evaluation (IP, CP, GKP), pp. 897–904.

DATE-2003-KranitisXGPZ #low cost #self

Low-Cost Software-Based Self-Testing of RISC Processor Cores (NK, GX, DG, AMP, YZ), pp. 10714–10719.

DATE-2001-Narita #game studies #multi

SH-4 RISC microprocessor for multimedia, game machine (SN), pp. 699–701.

LCTES-OM-2001-LeeEMC #embedded #energy

An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors (SL, AE, SLM, NC), pp. 1–10.

VLDB-2000-ChaudhuriW #architecture #database #self #towards

Rethinking Database System Architecture: Towards a Self-Tuning RISC-Style Database System (SC, GW), pp. 1–10.

CC-2000-Kim #compilation #embedded #optimisation

Advanced Compiler Optimization for Calm RISC8 Low-End Embedded Processor (DHK), pp. 173–188.

PLDI-1999-CooperM #embedded

Enhanced Code Compression for Embedded RISC Processors (KDC, NM), pp. 139–149.

DAC-1998-AlbrechtNR #benchmark #design #embedded #estimation #metric #performance

HW/SW CoVerification Performance Estimation and Benchmark for a 24 Embedded RISC Core Design (TWA, JN, SR), pp. 808–811.

DATE-1998-SalapuraG #co-evolution #design #fuzzy #hardware

Hardware/Software Co-Design of a Fuzzy RISC Processor (VS, MG), pp. 875–882.

LCTES-1998-Campbell #architecture #embedded

Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications (MC), p. 261.

SIGMOD-1996-Agarwal #algorithm #sorting

A Super Scalar Sort Algorithm for RISC Processors (RCA), pp. 240–246.

HPCA-1995-JohnRHC #architecture #performance

Program Balance and Its Impact on High Performance RISC Architectures (LKJ, VR, PTH, LDC), pp. 370–379.

DAC-1994-TeraiGNSO #automation #concept #design #performance

Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1 (HT, KG, YN, YS, YO), pp. 262–269.

SIGMOD-1994-NybergBCGL #named

AlphaSort: A RISC Machine Sort (CN, TB, ZC, JG, DBL), pp. 233–242.

DAC-1993-GanapathyA #pseudo

Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor (GG, JAA), pp. 550–555.

ASPLOS-1992-AndrewsS #migration #product line

Migrating a CISC Computer Family onto RISC via Object Code Translation (KA, DS), pp. 213–222.

HPDC-1992-BetelloRSR #clustering

Lattice Boltzmann Method on a Cluster of IBM RISC System/6000 Workstations (GB, GR, SS, FR), pp. 242–247.

ASPLOS-1991-BhandarkarC #architecture #hardware #performance

Performance From Architecture: Comparing a RISC and CISC with Similar Hardware Organization (DB, DWC), pp. 310–319.

ASPLOS-1991-BradleeEH #scheduling

Integrating Register Allocation and Instruction Scheduling for RISCs (DGB, SJE, RRH), pp. 122–131.

ASPLOS-1991-HallO #architecture #performance

Performance Characteristics of Architectural Features of the IBM RISC System/6000 (CBH, KO), pp. 303–309.

POPL-1990-PalemS #scheduling

Scheduling Time-Critical Instructions on RISC Machines (KVP, BBS), pp. 270–280.

CLP-1990-HarsatG90

An Extended RISC Methodology and its Application to FCP (AH, RG), pp. 67–82.

CLP-1990-Taylor90 #compilation #prolog

LIPS on a MIPS: Results from a Prolog Compiler for a RISC (AT), pp. 174–185.

DAC-1988-HenkelG #layout #named #set #verification

RISCE — A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification (VH, UG), pp. 465–470.

CCHSC-1988-Kroha #code generation

Code Generation for a RISC Machine (PK), pp. 204–214.

PLDI-1987-Clark #editing #interpreter #syntax

The JADE interpreter: a RISC interpreter for syntax directed editing (CFC), pp. 222–228.

PLDI-1987-DavidsonG #c #interpreter #named #programming language

Cint: a RISC interpreter for the C programming language (JWD, JVG), pp. 189–198.

FPCA-1987-Clarke #architecture #multi

The D-RISC: An architecture for use in multiprocessors (TJWC), pp. 16–33.

ASPLOS-1987-BorrielloCDN #case study #prolog

RISCs versus CISCs for Prolog: A Case Study (GB, ARC, PBD, MNN), pp. 136–145.

ASPLOS-1987-BushSUH #compilation

Compiling Smalltalk-80 to a RISC (WRB, ADS, DU, PNH), pp. 112–116.

ASPLOS-1987-Kieburtz #architecture #symbolic computation

A RISC Architecture for Symbolic Computation (RBK), pp. 146–155.