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Travelled to:
10 × USA
4 × France
4 × Germany
Collaborated with:
H.Lekatsas Y.Xie J.Henkel Y.Li K.Keutzer T.Lv C.H.Lin T.Lee T.Lee N.K.Jha W.Bower C.Seaquist J.Akella M.Mohiyuddin A.Prakash A.Aziz S.Saha J.Schlessman S.Puthenpurayil S.S.Bhattacharyya S.Yang N.Vijaykrishnan D.N.Serpanos J.Xu S.T.Chakradhar A.Takach C.Huang R.Manno E.Wu B.Liu A.Wolfe M.M.Yeung B.Yeo D.Markham E.Haritan T.Hattori H.Yagi P.G.Paulin A.Nohl D.Wingard M.Müller
Talks about:
system (8) synthesi (5) design (5) code (5) multiprocessor (4) compress (4) embed (4) chip (4) behavior (3) schedul (3)

Person: Wayne Wolf

DBLP DBLP: Wolf:Wayne

Contributed to:

DAC 20082008
DATE 20082008
DATE 20052005
DAC 20042004
DATE DF 20042004
DATE v2 20042004
DATE 20032003
DATE 20022002
DATE 20012001
DAC 20002000
DAC 19981998
DAC 19971997
ED&TC 19971997
DAC 19931993
DAC 19921992
DAC 19901990
DAC 19881988
PLDI 19881988
DAC 19861986
ADL 19951995

Wrote 26 papers:

DAC-2008-HaritanHYPWNWM #challenge #design #exclamation #manycore #question #what
Multicore design is the challenge! what is the solution? (EH, TH, HY, PGP, WW, AN, DW, MM), pp. 128–130.
DATE-2008-SahaSPBW #framework #implementation #message passing #parallel
An Optimized Message Passing Framework for Parallel Implementation of Signal Processing Applications (SS, JS, SP, SSB, WW), pp. 1220–1225.
DATE-2005-Wolf #multi
Multimedia Applications of Multiprocessor Systems-on-Chips (WW), pp. 86–89.
DATE-2005-YangWVSX #approach #design
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach (SY, WW, NV, DNS, YX), pp. 64–69.
DAC-2004-MohiyuddinPAW
Synthesizing interconnect-efficient low density parity check codes (MM, AP, AA, WW), pp. 488–491.
DAC-2004-Wolf #future of #multi
The future of multiprocessor systems-on-chips (WW), pp. 681–685.
DATE-DF-2004-LinXW #embedded
LZW-Based Code Compression for VLIW Embedded Systems (CHL, YX, WW), pp. 76–81.
DATE-v2-2004-XuWHCL #case study #design #embedded #video
A Case Study in Networks-on-Chip Design for Embedded Video (JX, WW, JH, STC, TL), pp. 770–777.
DATE-2003-LvHLW #encoding
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses (TL, JH, HL, WW), pp. 10542–10549.
DATE-2003-XieWL
Profile-Driven Selective Code Compression (YX, WW, HL), pp. 10462–10467.
DATE-2002-LeeWH #design #implementation #multi #platform #runtime
Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs (TML, WW, JH), pp. 296–301.
DATE-2002-LvWHL #adaptation #encoding #taxonomy
An Adaptive Dictionary Encoding Scheme for SOC Data Buses (TL, WW, JH, HL), pp. 1059–1064.
DATE-2001-XieW #graph #hardware #scheduling
Allocation and scheduling of conditional task graph in hardware/software co-synthesis (YX, WW), pp. 620–625.
DAC-2000-LekatsasHW #design #embedded #power management
Code compression for low power embedded system design (HL, JH, WW), pp. 294–299.
DAC-1998-LekatsasW #embedded
Code Compression for Embedded Systems (HL, WW), pp. 516–521.
DAC-1997-LiW #memory management #multi #synthesis
A Task-Level Hierarchical Memory Model for System Synthesis of Multiprocessors (YL, WW), pp. 153–156.
EDTC-1997-LiW #multi #scheduling
Hierarchical scheduling and allocation of multirate systems on heterogeneous multiprocessors (YL, WW), pp. 134–139.
DAC-1993-LeeJW #behaviour #synthesis
Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments (TCL, NKJ, WW), pp. 292–297.
DAC-1992-WolfTHMW #behaviour #synthesis
The Princeton University Behavioral Synthesis System (WW, AT, CYH, RM, EW), pp. 182–187.
DAC-1990-BowerSW #framework #generative #industrial #layout
A Framework for Industrial Layout Generators (WB, CS, WW), pp. 419–424.
DAC-1990-Wolf #automaton #behaviour #network #synthesis
The FSM Network Model for Behavioral Synthesis of Control-Dominated Machines (WW), pp. 692–697.
DAC-1988-WolfKA #algorithm #kernel #logic #multi
A Kernel-Finding State Assignment Algorithm for Multi-Level Logic (WW, KK, JA), pp. 433–438.
PLDI-1988-KeutzerW #compilation #hardware
Anatomy of a Hardware Compiler (KK, WW), pp. 95–104.
DAC-1986-Wolf #database #object-oriented
An object-oriented, procedural database for VLSI chip planning (WW), pp. 744–751.
ADL-1995-WolfLWYYM #library #video
Video as Scholary Material in the Digital Library (WW, BL, AW, MMY, BLY, DM), pp. 45–53.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.