Travelled to:7 × USA
Collaborated with:C.J.Alpert S.T.Quay M.Mani M.Orshansky T.V.Nguyen O.J.Nastov M.W.Beattie H.Zheng B.Krauter R.R.Rao D.Blaauw D.Sylvester F.Liu C.V.Kashyap S.S.Sapatnekar E.Haritan K.Keutzer D.Kirkpatrick S.Meier D.Pryor T.Spyrou
Talks about:insert (3) buffer (3) delay (3) distribut (2) comput (2) yield (2) interconnect (1) constraint (1) transient (1) processor (1)
Person: Anirudh Devgan
DBLP: Devgan:Anirudh
Contributed to:
2008200520042003199919981997Wrote 9 papers:
- DAC-2008-SapatnekarHKDKMPS #manycore
- Reinventing EDA with manycore processors (SSS, EH, KK, AD, DK, SM, DP, TS), pp. 126–127.
- DAC-2005-BeattieZDK #3d #distributed #modelling
- Spatially distributed 3D circuit models (MWB, HZ, AD, BK), pp. 153–158.
- DAC-2005-ManiDO #algorithm #constraints #performance #statistics
- An efficient algorithm for statistical minimization of total power under timing yield constraints (MM, AD, MO), pp. 309–314.
- DAC-2004-RaoDBS #estimation #parametricity #variability
- Parametric yield estimation considering leakage variability (RRR, AD, DB, DS), pp. 442–447.
- DAC-2003-AlpertLKD #metric #using
- Delay and slew metrics using the lognormal distribution (CJA, FL, CVK, AD), pp. 382–385.
- DAC-1999-AlpertDQ
- Buffer Insertion with Accurate Gate and Interconnect Delay Computation (CJA, AD, STQ), pp. 479–484.
- DAC-1998-AlpertDQ #optimisation
- Buffer Insertion for Noise and Delay Optimization (CJA, AD, STQ), pp. 362–367.
- DAC-1998-NguyenDN #linear #simulation
- Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation (TVN, AD, OJN), pp. 477–482.
- DAC-1997-AlpertD
- Wire Segmenting for Improved Buffer Insertion (CJA, AD), pp. 588–593.