BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × France
2 × Germany
8 × USA
Collaborated with:
Y.Cao S.R.Nassif P.Feldmann B.R.Hodges Y.Ye M.Chen C.V.Kashyap D.G.Drmanac L.Wang S.B.K.Vrudhula W.Zhao G.Venkataraman J.Hu C.C.N.Sze C.J.Alpert A.Devgan H.Su D.Widiger B.Krauter P.Li X.Li L.T.Pileggi R.Singhal A.Balijepalli A.R.Subramaniam K.Agarwal D.Sylvester D.Blaauw W.Wang S.Yang S.Bhardwaj R.Vattikonda
Talks about:
model (6) analysi (5) variabl (4) interconnect (3) circuit (3) method (3) simul (3) nois (3) lithographi (2) statist (2)

Person: Frank Liu

DBLP DBLP: Liu:Frank

Contributed to:

DAC 20142014
DAC 20122012
DAC 20092009
DAC 20082008
DAC 20072007
DATE 20072007
DATE 20062006
DAC 20052005
DATE 20052005
DAC 20042004
DAC 20032003

Wrote 15 papers:

A Time-Unrolling Method to Compute Sensitivity of Dynamic Systems (FL, PF), p. 6.
DAC-2012-LiuH #network #scalability #simulation
Dynamic river network simulation at large scale (FL, BRH), pp. 723–728.
DAC-2009-DrmanacLW #predict #process #variability
Predicting variability in nanoscale lithography processes (DGD, FL, LCW), pp. 545–550.
DAC-2009-YeLCC #analysis #layout #process #variability
Variability analysis under layout pattern-dependent rapid-thermal annealing process (YY, FL, MC, YC), pp. 551–556.
DAC-2008-YeLNC #modelling #simulation #statistics
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness (YY, FL, SRN, YC), pp. 900–905.
DAC-2007-Liu #correlation #design #framework #modelling
A General Framework for Spatial Correlation Modeling in VLSI Design (FL), pp. 817–822.
DAC-2007-SinghalBSLNC #analysis #modelling #simulation
Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation (RS, AB, ARS, FL, SRN, YC), pp. 823–828.
DAC-2007-WangYBVVLC #performance
The Impact of NBTI on the Performance of Combinational and Sequential Circuits (WW, SY, SB, RV, SBKV, FL, YC), pp. 364–369.
DATE-2007-ChenZLC #analysis #performance #statistics
Fast statistical circuit analysis with finite-point based transistor model (MC, WZ, FL, YC), pp. 1391–1396.
A practical method to estimate interconnect responses to variabilities (FL), pp. 545–546.
DATE-2006-VenkataramanHLS #optimisation
Integrated placement and skew optimization for rotary clocking (GV, JH, FL, CCNS), pp. 756–761.
DAC-2005-SuWKLK #analysis #effectiveness #embedded #functional #performance
A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis (HS, DW, CVK, FL, BK), pp. 186–189.
DATE-2005-LiLLPN #modelling #order #parametricity #performance #reduction #using #variability
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction (PL, FL, XL, LTP, SRN), pp. 958–963.
DAC-2004-AgarwalSBLNV #analysis #metric
Variational delay metrics for interconnect timing analysis (KA, DS, DB, FL, SRN, SBKV), pp. 381–384.
DAC-2003-AlpertLKD #metric #using
Delay and slew metrics using the lognormal distribution (CJA, FL, CVK, AD), pp. 382–385.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.