BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × Germany
10 × USA
2 × France
Collaborated with:
M.Mani W.Wang Y.Wang C.Caramanis A.Bandyopadhyay K.Keutzer A.K.Singh S.R.Nassif K.He A.Gerstlauer V.Kreinovich A.Devgan J.C.Chen C.Hu M.Yousofshahi K.Lee S.Hassoun R.Puri M.Ceberio G.Xiang S.Banerjee K.B.Agarwal C.N.Sze A.Ramalingam D.Z.Pan M.Li X.Yi Z.Song K.Constantinides S.Plaza J.A.Blome B.Zhang V.Bertacco S.A.Mahlke T.M.Austin
Talks about:
time (7) statist (5) analysi (4) base (4) uncertainti (3) under (3) toler (3) probabilist (2) methodolog (2) effici (2)

Person: Michael Orshansky

DBLP DBLP: Orshansky:Michael

Contributed to:

DAC 20152015
DAC 20142014
DAC 20132013
DATE 20112011
DATE 20102010
DAC 20072007
DAC 20062006
HPCA 20062006
SAC 20062006
DAC 20052005
DAC 20042004
DAC 20022002
DAC 19981998

Wrote 14 papers:

DAC-2015-WangLYSOC #grid #novel #power management #reduction
Novel power grid reduction method based on L1 regularization (YW, ML, XY, ZS, MO, CC), p. 6.
DAC-2014-WangOC #optimisation #performance #polynomial #synthesis
Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization (YW, MO, CC), p. 6.
DAC-2013-YousofshahiOLH #capacity #identification #nondeterminism
Gene modification identification under flux capacity uncertainty (MY, MO, KL, SH), p. 5.
DATE-2011-HeGO #design #energy
Controlled timing-error acceptance for low energy IDCT design (KH, AG, MO), pp. 758–763.
DATE-2010-BanerjeeASNO #design
A methodology for propagating design tolerances to shape tolerances for use in manufacturing (SB, KBA, CNS, SRN, MO), pp. 1273–1278.
DAC-2007-RamalingamSNOP #analysis #composition #modelling #using
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis (AR, AKS, SRN, MO, DZP), pp. 148–153.
DAC-2006-SinghMPO #nondeterminism #runtime
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty (AKS, MM, RP, MO), pp. 522–527.
DAC-2006-WangKO #nondeterminism #parametricity #probability #statistics
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty (WSW, VK, MO), pp. 161–166.
HPCA-2006-ConstantinidesPBZBMAO #architecture #named
BulletProof: a defect-tolerant CMP switch architecture (KC, SP, JAB, BZ, VB, SAM, TMA, MO), pp. 5–16.
SAC-2006-OrshanskyWCX #analysis #robust #statistics
Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips (MO, WSW, MC, GX), pp. 1645–1649.
DAC-2005-ManiDO #algorithm #constraints #performance #statistics
An efficient algorithm for statistical minimization of total power under timing yield constraints (MM, AD, MO), pp. 309–314.
DAC-2004-OrshanskyB #analysis #correlation #performance #statistics
Fast statistical timing analysis handling arbitrary delay correlations (MO, AB), pp. 337–342.
DAC-2002-OrshanskyK #analysis #framework #probability
A general probabilistic framework for worst case timing analysis (MO, KK), pp. 556–561.
DAC-1998-OrshanskyCH #performance #simulation #statistics
A Statistical Performance Simulation Methodology for VLSI Circuits (MO, JCC, CH), pp. 402–407.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.