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Travelled to:
1 × France
17 × USA
Collaborated with:
Z.Li A.B.Kahng C.C.N.Sze A.Devgan J.Hu S.T.Quay N.Viswanathan P.Villarrubia S.Hu Y.Wei S.S.Sapatnekar G.Nam S.Yao H.Ren W.Shi J.Huang M.D.Moffitt D.A.Papa Q.Wang D.Z.Pan M.Hrkic F.Liu C.V.Kashyap T.F.Chan D.J.Huang I.L.Markov K.Yan N.Y.Zhou T.Jindal C.B.Winn C.C.N.Chu W.Liu Y.Li S.K.Karandikar L.N.Reddy A.D.Huber G.E.Téllez D.Keller
Talks about:
buffer (8) insert (5) placement (4) partit (4) design (4) time (4) driven (3) delay (3) wire (3) routabl (2)

Person: Charles J. Alpert

DBLP DBLP: Alpert:Charles_J=

Contributed to:

DAC 20132013
DATE 20132013
DAC 20122012
DAC 20102010
DAC 20092009
DAC 20082008
DAC 20072007
DAC 20062006
DAC 20052005
DAC 20042004
DAC 20032003
DAC 20012001
DAC 19991999
DAC 19981998
DAC 19971997
DAC 19951995
DAC 19941994
DAC 19931993

Wrote 24 papers:

DAC-2013-LiuWSALLV #constraints #design #estimation
Routing congestion estimation with real design constraints (WHL, YW, CCNS, CJA, ZL, YLL, NV), p. 8.
DATE-2013-WeiLSHAS #design #effectiveness #named
CATALYST: planning layer directives for effective design closure (YW, ZL, CCNS, SH, CJA, SSS), pp. 1873–1878.
DAC-2012-LiANSVZ #design #physics #predict
Guiding a physical design closure system to produce easier-to-route designs with more predictable timing (ZL, CJA, GJN, CCNS, NV, NYZ), pp. 465–470.
DAC-2012-ViswanathanASLW #benchmark #contest #metric
The DAC 2012 routability-driven placement contest and benchmark suite (NV, CJA, CCNS, ZL, YW), pp. 774–782.
DAC-2012-WeiSVLARHTKS #evaluation #named
GLARE: global and local wiring aware routability evaluation (YW, CCNS, NV, ZL, CJA, LNR, ADH, GET, DK, SSS), pp. 768–773.
DAC-2010-JindalAHLNW #detection #logic
Detecting tangled logic structures in VLSI netlists (TJ, CJA, JH, ZL, GJN, CBW), pp. 603–608.
DAC-2009-HuLA #approximate #polynomial
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion (SH, ZL, CJA), pp. 424–429.
DAC-2008-MoffittPLA #optimisation
Path smoothing via discrete optimization (MDM, DAP, ZL, CJA), pp. 724–727.
DAC-2007-ViswanathanNAVRC #named #polynomial
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization (NV, GJN, CJA, PV, HR, CCNC), pp. 453–458.
Timing-driven Steiner trees are (practically) free (CJA, ABK, CCNS, QW), pp. 389–392.
DAC-2006-HuAHKLSS #algorithm #performance
Fast algorithms for slew constrained minimum cost buffering (SH, CJA, JH, SKK, ZL, WS, CCNS), pp. 308–313.
DAC-2005-RenPAV #migration
Diffusion-based placement migration (HR, DZP, CJA, PV), pp. 515–520.
Path based buffer insertion (CCNS, CJA, JH, WS), pp. 509–514.
DAC-2004-AlpertHHQ #flexibility #layout #performance #physics
Fast and flexible buffer trees that navigate the physical layout environment (CJA, MH, JH, STQ), pp. 24–29.
DAC-2003-AlpertLKD #metric #using
Delay and slew metrics using the lognormal distribution (CJA, FL, CVK, AD), pp. 382–385.
DAC-2001-AlpertHSV #resource management
A Practical Methodology for Early Buffer and Wire Resource Allocation (CJA, JH, SSS, PV), pp. 189–194.
Buffer Insertion with Accurate Gate and Interconnect Delay Computation (CJA, AD, STQ), pp. 479–484.
DAC-1998-AlpertDQ #optimisation
Buffer Insertion for Noise and Delay Optimization (CJA, AD, STQ), pp. 362–367.
DAC-1997-AlpertCHMY #polynomial #revisited
Quadratic Placement Revisited (CJA, TFC, DJHH, ILM, KY), pp. 752–757.
Wire Segmenting for Improved Buffer Insertion (CJA, AD), pp. 588–593.
DAC-1997-AlpertHK #clustering #multi
Multilevel Circuit Partitioning (CJA, JHH, ABK), pp. 530–533.
DAC-1995-AlpertY #clustering
Spectral Partitioning: The More Eigenvectors, The Better (CJA, SZY), pp. 195–200.
DAC-1994-AlpertK #clustering #multi #programming
Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming (CJA, ABK), pp. 652–657.
DAC-1993-AlpertK #clustering #geometry #multi #performance
Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning (CJA, ABK), pp. 743–748.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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