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Travelled to:
1 × Denmark
3 × Germany
7 × France
7 × USA
Collaborated with:
L.Hedrich M.Olbrich W.Hartong T.Adler M.Ringe T.Lindenkreuz P.Leppelt J.Abke J.Küter R.Popp A.Rein C.Borchers F.Luellau T.Hoepken H.Harizi R.HauBler L.Näthke V.Burkhay J.Oehmen H.Brocke C.Katzschke M.Sohn V.M.z.Bexten M.Tristl M.Zhang D.Seider M.Frerichs H.Kinzelbach D.Grabowski H.Gräb S.Heinen S.Steinhorst Y.Wang
Talks about:
analog (11) circuit (8) model (8) nonlinear (7) verif (6) analysi (5) approach (4) system (4) driven (4) algorithm (3)

Person: Erich Barke

DBLP DBLP: Barke:Erich

Contributed to:

DATE 20142014
DATE 20092009
DATE 20082008
DAC 20072007
DATE 20072007
DATE v1 20042004
DATE v2 20042004
CAV 20022002
DAC 20022002
DATE 20022002
DATE 20012001
DAC 20002000
DATE 20002000
DATE 19981998
DAC 19961996
DAC 19851985
DAC 19841984
DAC 19831983

Wrote 23 papers:

DATE-2014-KatzschkeSOBTB #constraints #design
Application of Mission Profiles to enable cross-domain constraint-driven design (CK, MPS, MO, VMzB, MT, EB), pp. 1–6.
DATE-2009-BarkeGGHHPSW #formal method #verification
Formal approaches to analog circuit verification (EB, DG, HG, LH, SH, RP, SS, YW), pp. 724–729.
DATE-2008-LeppeltB #complexity
Determining the Technical Complexity of Integrated Circuits (PL, EB), p. 935.
DAC-2007-HariziHOB #analysis #modelling #performance
Efficient Modeling Techniques for Dynamic Voltage Drop Analysis (HH, RH, MO, EB), pp. 706–711.
DATE-2007-ZhangOSFKB #analysis #approach #named #parametricity #process
CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions (MZ, MO, DS, MF, HK, EB), pp. 243–248.
DATE-v1-2004-NathkeBHB #automation #behaviour #generative
Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques (LN, VB, LH, EB), pp. 442–447.
DATE-v2-2004-OlbrichB #locality #probability #using
Placement Using a Localization Probability Model (LPM) (MO, EB), p. 1412.
CAV-2002-HartongHB #model checking #modelling #on the
On Discrete Modeling and Model Checking for Nonlinear Analog Systems (WH, LH, EB), pp. 401–413.
DAC-2002-HartongHB #algorithm #model checking #verification
Model checking algorithms for analog verification (WH, LH, EB), pp. 542–547.
DATE-2002-AbkeB #automaton #implementation
A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs (JA, EB), p. 1085.
DATE-2002-HartongHB #approach #model checking
An Approach to Model Checking for Nonlinear Analog Systems (WH, LH, EB), p. 1080.
DATE-2002-PoppOHB #analysis #automation #parametricity
Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits (RP, JO, LH, EB), pp. 274–278.
DATE-2001-KuterB #architecture #clustering
Architecture driven partitioning (JK, EB), pp. 479–487.
DATE-2001-OlbrichRB #algorithm #analysis #classification
An improved hierarchical classification algorithm for structural analysis of integrated circuits (MO, AR, EB), p. 807.
DAC-2000-AdlerBHB #verification
A current driven routing and verification methodology for analog applications (TA, HB, LH, EB), pp. 385–389.
DATE-2000-AdlerB #multi
Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications (TA, EB), pp. 446–450.
DATE-2000-RingeLB #analysis
Static Timing Analysis Taking Crosstalk into Account (MR, TL, EB), pp. 451–455.
DATE-1998-HedrichB #approach #formal method #linear #parametricity #verification
A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances (LH, EB), pp. 649–654.
DATE-1998-RingeLB #satisfiability #using #verification
Path Verification Using Boolean Satisfiability (MR, TL, EB), pp. 965–966.
DAC-1996-BorchersHB #behaviour #equation #generative
Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits (CB, LH, EB), pp. 236–239.
DAC-1985-Barke #finite
Resistance calculation from mask artwork data by finite element method (EB), pp. 305–311.
DAC-1984-LuellauHB #algorithm #independence
A technology independent block extraction algorithm (FL, TH, EB), pp. 610–615.
DAC-1983-Barke #layout #verification
A layout verification system for analog bipolar integrated circuits (EB), pp. 353–359.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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