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Travelled to:
1 × USA
3 × Germany
4 × France
Collaborated with:
L.Benini G.D.Micheli I.Loi S.Carta L.Raffo D.Bertozzi M.H.B.Jamaa D.Atienza P.Meloni M.Loghi R.Zafalon C.Seiculescu S.Murali A.Pullini J.Ceng R.Leupers F.Ferrari C.Ferri S.Mahadevan M.Storgaard R.G.Olsen J.Sparsø J.Madsen S.Stergiou A.Ibrahim P.Hager A.Bartolini M.Arditi
Talks about:
network (5) chip (4) design (3) synthesi (2) mpsoc (2) tabl (2) no (2) interconnect (1) ultrasound (1) bottleneck (1)

Person: Federico Angiolini

DBLP DBLP: Angiolini:Federico

Contributed to:

DATE 20152015
DAC 20102010
DATE 20092009
DATE 20082008
DATE 20072007
DATE 20062006
DATE 20052005
DATE v2 20042004

Wrote 10 papers:

DATE-2015-IbrahimHBAABM #3d
Tackling the bottleneck of delay tables in 3D ultrasound imaging (AI, PH, AB, FA, MA, LB, GDM), pp. 1683–1688.
DAC-2010-MicheliSMBAP #network #research
Networks on Chips: from research to products (GDM, CS, SM, LB, FA, AP), pp. 300–305.
DATE-2009-LoiAB #configuration management #interface #network #synthesis
Synthesis of low-overhead configurable source routing tables for network interfaces (IL, FA, LB), pp. 262–267.
DATE-2008-LoiAB #3d
Developing Mesochronous Synchronizers to Enable 3D NoCs (IL, FA, LB), pp. 1414–1419.
DATE-2007-AngioliniJABM #design #fault tolerance #interactive
Interactive presentation: Improving the fault tolerance of nanometric PLA designs (FA, MHBJ, DA, LB, GDM), pp. 570–575.
DATE-2006-AngioliniCLFFB #design #framework
An integrated open framework for heterogeneous MPSoC design space exploration (FA, JC, RL, FF, CF, LB), pp. 1145–1150.
DATE-2006-AngioliniMCBR #layout
Contrasting a NoC and a traditional interconnect fabric with layout awareness (FA, PM, SC, LB, LR), pp. 124–129.
DATE-2005-MahadevanASOSM #generative #network #performance #simulation
A Network Traffic Generator Model for Fast Network-on-Chip Simulation (SM, FA, MS, RGO, JS, JM), pp. 780–785.
DATE-2005-StergiouACRBM #abstract syntax tree #design #library #network #pipes and filters #synthesis
ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips (SS, FA, SC, LR, DB, GDM), pp. 1188–1193.
DATE-v2-2004-LoghiABBZ #communication
Analyzing On-Chip Communication in a MPSoC Environment (ML, FA, DB, LB, RZ), pp. 752–757.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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