BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
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Travelled to:
1 × France
1 × Germany
1 × Spain
4 × USA
Collaborated with:
N.S.Kim M.Erez W.J.Dally J.Kim S.Yoo S.Lee S.Choo A.F.Farahani K.Morrow Y.Choi N.Jayasena H.Wang C.Park G.Byun D.Kim H.Jung Y.H.Son S.Lee O.Seongil S.Kwon K.Chen S.Li N.Muralimanohar J.B.Brockman N.P.Jouppi WonJun Song G.Kim Hyungjoon Jung Jongwook Chung J.W.Lee
Talks about:
architectur (5) dram (4) memori (3) cach (3) processor (2) parallel (2) perform (2) network (2) access (2) stack (2)

Person: Jung Ho Ahn

DBLP DBLP: Ahn:Jung_Ho

Contributed to:

HPCA 20152015
DATE 20122012
HPCA 20122012
DAC 20112011
DATE 20112011
HPCA 20052005
HPCA 20042004
ASPLOS 20172017

Wrote 10 papers:

HPCA-2015-FarahaniAMK #architecture #memory management #named #standard
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules (AFF, JHA, KM, NSK), pp. 283–295.
HPCA-2015-SonLSKKA #architecture #named
CiDRA: A cache-inspired DRAM resilience architecture (YHS, SL, OS, SK, NSK, JHA), pp. 502–513.
HPCA-2015-WangPBAK #alloy #architecture #memory management #named
Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems (HW, CJP, GB, JHA, NSK), pp. 296–308.
DATE-2012-ChenLMABJ #3d #architecture #in memory #memory management #modelling #named
CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory (KC, SL, NM, JHA, JBB, NPJ), pp. 33–38.
HPCA-2012-AhnCK #approach #architecture #network #scalability
Network within a network approach to create a scalable high-radix router microarchitecture (JHA, SC, JK), pp. 455–466.
DAC-2011-ChoiYLA #behaviour #fault #performance
Matching cache access behavior and bit error pattern for high performance low Vcc L1 cache (YGC, SY, SL, JHA), pp. 978–983.
DATE-2011-KimYLAJ #3d #analysis #embedded #mobile #performance
A quantitative analysis of performance benefits of 3D die stacking on mobile and embedded SoC (DK, SY, SL, JHA, HJ), pp. 1333–1338.
HPCA-2005-AhnED #architecture #parallel
Scatter-Add in Data Parallel Architectures (JHA, ME, WJD), pp. 132–142.
Stream Register Files with Indexed Access (NJ, ME, JHA, WJD), pp. 60–72.
History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers (WS, GK, HJ, JC, JHA, JWL, JK), pp. 765–777.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.