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Travelled to:
1 × China
1 × France
1 × Spain
7 × USA
Collaborated with:
D.H.Yoon W.J.Dally M.Rhu J.H.Ahn D.Kim Haishan Zhu M.K.Jeong J.Kim M.Sullivan C.Sudanthi N.C.Paver N.Jayasena D.Sunwoo M.Sullivan I.Lee N.Muralimanohar J.Chang P.Ranganathan N.P.Jouppi S.Jourdan L.Rappoport Y.Almog A.Yoaz R.Ronen D.Li D.R.Johnson M.O'Connor D.Burger D.S.Fussell S.W.Redder T.J.Knight J.Y.Park M.Ren M.Houston K.Fatahalian A.Aiken P.Hanrahan
Talks about:
memori (6) balanc (3) parallel (2) reliabl (2) flexibl (2) control (2) system (2) share (2) free (2) cach (2)

Person: Mattan Erez

DBLP DBLP: Erez:Mattan

Contributed to:

HPCA 20152015
HPCA 20132013
DAC 20122012
HPCA 20122012
HPCA 20112011
ASPLOS 20102010
PPoPP 20072007
HPCA 20052005
HPCA 20042004
HPCA 20002000
ASPLOS 20162016

Wrote 13 papers:

HPCA-2015-KimE #performance #reliability #trade-off
Balancing reliability, cost, and performance tradeoffs with FreeFault (DWK, ME), pp. 439–450.
HPCA-2015-KimSE #flexibility #memory management #reliability
Bamboo ECC: Strong, safe, and flexible codes for reliable computer memory (JK, MS, ME), pp. 101–112.
HPCA-2015-LiRJOEBFR #throughput
Priority-based cache allocation in throughput processors (DL, MR, DRJ, MO, ME, DB, DSF, SWR), pp. 89–100.
HPCA-2013-RhuE #control flow #execution #gpu #performance
The dual-path execution model for efficient GPU control flow (MR, ME), pp. 591–602.
DAC-2012-JeongESP #cpu #gpu #memory management
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC (MKJ, ME, CS, NCP), pp. 850–855.
HPCA-2012-JeongYSSLE #locality #memory management #parallel
Balancing DRAM locality and parallelism in shared memory CMP systems (MKJ, DHY, DS, MS, IL, ME), pp. 53–64.
HPCA-2011-YoonMCRJE #fault #memory management #named
FREE-p: Protecting non-volatile memory against both hard and soft errors (DHY, NM, JC, PR, NPJ, ME), pp. 466–477.
ASPLOS-2010-YoonE #flexibility #in memory #memory management
Virtualized and flexible ECC for main memory (DHY, ME), pp. 397–408.
PPoPP-2007-KnightPRHEFADH #compilation #memory management
Compilation for explicitly managed memory hierarchies (TJK, JYP, MR, MH, ME, KF, AA, WJD, PH), pp. 226–236.
HPCA-2005-AhnED #architecture #parallel
Scatter-Add in Data Parallel Architectures (JHA, ME, WJD), pp. 132–142.
Stream Register Files with Indexed Access (NJ, ME, JHA, WJD), pp. 60–72.
eXtended Block Cache (SJ, LR, YA, ME, AY, RR), pp. 61–70.
ASPLOS-2016-ZhuE #manycore #named
Dirigent: Enforcing QoS for Latency-Critical Tasks on Shared Multicore Systems (HZ, ME), pp. 33–47.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.