BibSLEIGH — Lars

Travelled to:

3 × Germany
4 × France
4 × USA

Collaborated with:

J.Henkel M.Shafique F.Hameed W.Ahmed H.Zhang S.Kobbe A.Grudnitsky F.Samie C.Hsieh S.Kreutz S.Kramer S.Rehman M.U.K.Khan J.M.Borrmann M.A.Kochte M.E.Imhof H.Wunderlich R.König T.Stripf J.Becker N.Dutt P.Gupta S.R.Nassif M.B.Tahoori N.Wehn

Talks about:

reconfigur (6) multi (6) time (6) run (6) architectur (5) processor (5) instruct (5) system (5) cach (5) set (5)

Person: Lars Bauer

DBLP: Bauer:Lars

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

Wrote 19 papers:

DATE-2015-KobbeBH #adaptation #modelling #on the fly #performance: Adaptive on-the-fly application performance modeling for many cores (SK, LB, JH), pp. 730–735.
DATE-2015-SamieBHH #multi #online: Online binding of applications to multiple clock domains in shared FPGA-based systems (FS, LB, CMH, JH), pp. 25–30.
DAC-2014-HameedBH #architecture #latency #novel: Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture (FH, LB, JH), p. 6.
DAC-2014-HenkelBZRS #architecture #dependence #multi: Multi-Layer Dependability: From Microarchitecture to Application Level (JH, LB, HZ, SR, MS), p. 6.
DAC-2014-ZhangKIBWH #configuration management #named #reliability: GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems (HZ, MAK, MEI, LB, HJW, JH), p. 6.
DAC-2013-HenkelBDGNSTW #lessons learnt #reliability #roadmap: Reliable on-chip systems in the nano-era: lessons learnt and future trends (JH, LB, ND, PG, SRN, MS, MBT, NW), p. 10.
DATE-2013-HameedBH #adaptation #multi: Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores (FH, LB, JH), pp. 77–82.
DATE-2013-KhanBBSH #video: An H.264 Quad-FullHD low-latency intra video encoder (MUKK, JMB, LB, MS, JH), pp. 115–120.
DATE-2012-GrudnitskyBH #architecture #configuration management: Partial online-synthesis for mixed-grained reconfigurable architectures (AG, LB, JH), pp. 1555–1560.
DATE-2012-HameedBH #adaptation #architecture #manycore #runtime: Dynamic cache management in multi-core architectures through run-time adaptation (FH, LB, JH), pp. 485–490.
DATE-2011-AhmedSBH #configuration management #multi #named #runtime: mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions (WA, MS, LB, JH), pp. 1554–1559.
DATE-2011-ShafiqueBAH #configuration management #manycore #resource management #runtime: Minority-Game-based resource allocation for run-time reconfigurable multi-core processors (MS, LB, WA, JH), pp. 1261–1266.
DATE-2010-KoenigBSSABH #architecture #configuration management #multi #named #novel: KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture (RK, LB, TS, MS, WA, JB, JH), pp. 819–824.
DATE-2010-ShafiqueBH #adaptation #energy #estimation #named #predict #runtime #video: enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder (MS, LB, JH), pp. 1725–1730.
DATE-2009-BauerSH #architecture #configuration management #design: Cross-architectural design space exploration tool for reconfigurable processors (LB, MS, JH), pp. 958–963.
DATE-2009-ShafiqueBH #approach #design #hardware #parallel #performance #predict #video: A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec (MS, LB, JH), pp. 1434–1439.
DAC-2008-BauerSH #embedded #runtime #set: Run-time instruction set selection in a transmutable embedded processor (LB, MS, JH), pp. 56–61.
DATE-2008-BauerSKH #embedded #runtime #set: Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set (LB, MS, SK, JH), pp. 752–757.
DAC-2007-BauerSKH #framework #named #platform #set: RISPP: Rotating Instruction Set Processing Platform (LB, MS, SK, JH), pp. 791–796.