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Travelled to:
1 × Portugal
1 × USA
3 × France
6 × Germany
Collaborated with:
M.Hübner T.Stripf R.König S.Werner O.Sander K.D.Müller-Glaser B.Glas A.Herkersdorf C.Schmutzler M.Simons K.Paulsson M.Ullmann W.Jin J.Heisswolf A.Azarian J.M.P.Cardoso M.Traub T.Streichert O.Krasovytskyy A.Thomas M.Vorbach V.Baumgarten J.Henkel O.Oey D.Göhringer C.Roth A.Klimm C.Tradowsky T.Gädeke T.Bruckschlögl W.Stork C.Pham-Quoc Z.Al-Ars K.Bertels R.Esser W.Stechele V.Lauer L.Bauer M.Shafique W.Ahmed J.Meyer J.Noguera L.Braun R.M.Gil R.Stewart A.Zaib A.Zwinkau S.Kobbe A.Weichslgartner J.Teich G.Snelting T.Sandmann V.V.Duy S.Bähr F.Bapp H.Michel D.Kaule D.Adam E.Lübbers J.Hairbucher A.Richter C.Herber A.Deledda C.Mucci A.Vitkovski P.Bonnot A.Grasset P.Millet M.Kühnle F.Ries M.Coppola L.Pieralisi R.Locatelli G.Maruccia F.Campi T.DeMarco
Talks about:
system (8) base (7) reconfigur (6) architectur (5) communic (4) design (4) heterogen (3) hardwar (3) automot (3) integr (3)

Person: Jürgen Becker

DBLP DBLP: Becker:J=uuml=rgen

Contributed to:

DAC 20142014
DATE 20142014
PDP 20142014
DATE 20132013
SAC 20132013
DATE 20122012
DATE 20112011
DATE 20102010
DATE 20092009
DATE 20082008
DATE 20052004
DATE 20032003

Wrote 19 papers:

DAC-2014-HeisswolfZZKWTHSHB #communication #named #programming
CAP: Communication Aware Programming (JH, AZ, AZ, SK, AW, JT, JH, GS, AH, JB), p. 6.
DATE-2014-SanderSDBBBMKALHRHH #hardware #manycore
Hardware virtualization support for shared resources in mixed-criticality multicore systems (OS, TS, VVD, SB, FB, JB, HUM, DK, DA, EL, JH, AR, CH, AH), pp. 1–6.
PDP-2014-TradowskyGBSMB #adaptation #concept #locality #named #power management
SmartLoCore: A Concept for an Adaptive Power-Aware Localization Processor (CT, TG, TB, WS, KDMG, JB), pp. 478–481.
DATE-2013-Pham-QuocHWABB #design #hardware #hybrid
Hybrid interconnect design for heterogeneous hardware accelerators (CPQ, JH, SW, ZAA, JB, KB), pp. 843–846.
SAC-2013-AzarianCWB #approach #manycore #pipes and filters
An FPGA-based multi-core approach for pipelining computing stages (AA, JMPC, SW, JB), pp. 1533–1540.
DATE-2012-SchmutzlerSB #on the
On demand dependent deactivation of automotive ECUs (CS, MS, JB), pp. 69–74.
DATE-2012-StripfKB #approximate #architecture
A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture (TS, RK, JB), pp. 21–26.
DATE-2012-WernerOGHB #configuration management #distributed #manycore
Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems (SW, OO, DG, MH, JB), pp. 280–283.
DATE-2011-MeyerNHBSGSB #configuration management #performance #using
Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration (JM, JN, MH, LB, OS, RMG, RS, JB), pp. 1542–1547.
DATE-2010-KoenigBSSABH #architecture #configuration management #multi #named #novel
KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture (RK, LB, TS, MS, WA, JB, JH), pp. 819–824.
DATE-2010-TraubSKB #network
Scenario extraction for a refined timing-analysis of automotive network topologies (MT, TS, OK, JB), pp. 81–86.
DATE-2009-SanderGRBM #communication
Priority-based packet communication on a bus-shaped structure for FPGA-systems (OS, BG, CR, JB, KDMG), pp. 178–183.
DATE-2008-BeckerHEHSL #architecture #communication #design
Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems (JB, MH, RE, AH, WS, VL).
DATE-2008-DeleddaMVBGMKRHBCPLMCD #communication #configuration management #design #framework
Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor (AD, CM, AV, PB, AG, PM, MK, FR, MH, JB, MC, LP, RL, GM, FC, TD), pp. 1352–1357.
DATE-2008-GlasKSMB #architecture #configuration management
A System Architecture for Reconfigurable Trusted Platforms (BG, AK, OS, KDMG, JB), pp. 541–544.
DATE-2008-KoenigSB #algorithm #novel #recursion
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms (RK, TS, JB), pp. 604–609.
DATE-2008-PaulssonHB #integration #metric #power management
Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs (KP, MH, JB), pp. 50–55.
DATE-2005-UllmannJB04 #configuration management #hardware
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems (MU, WJ, JB), pp. 259–264.
DATE-2003-BeckerTVB #architecture #configuration management #industrial #integration
An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration (JB, AT, MV, VB), pp. 11120–11121.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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