BibSLEIGH — Norbert

Travelled to:

10 × France
2 × USA
8 × Germany

Collaborated with:

C.Weis F.Kienle T.Brack B.Akesson K.Goossens M.May L.Benini B.Wurth M.Alles A.Worm K.Chandrasekar S.Scholl I.Loi T.Vogt S.Hein M.Münch M.Glesner C.d.Schryver P.Torruella D.Schmidt M.Berning F.Berens G.Kreiselmaier F.Gilbert M.J.Thul H.Lamm M.Jung S.Goossens M.Koedam R.Leupers T.Ilnseher W.Raab H.Michel J.Schuck G.Kamp L.Fanucci A.Herkersdorf S.R.Nassif C.Brugger J.A.Varela S.Tang R.Korn M.Sadri M.D.Gomony R.Mehra J.Sproch K.Caesar P.Mann A.Roth S.Müller M.Schreger M.Kabutz P.Ehses C.Santos P.Vivet M.Roodzant J.Stahl A.Cohen B.Janson J.Henkel L.Bauer N.Dutt P.Gupta M.Shafique M.B.Tahoori A.Bouajila J.Zeppenfeld W.Stechele D.Ziener J.Teich U.Schlichtmann V.Kleeberger J.A.Abraham A.Evans C.Gimmler-Dumont M.Glaß T.Lehnigk-Emden N.E.L'Insalata F.Rossi M.Rovini

Talks about:

decod (12) dram (9) system (8) design (6) code (6) level (5) ldpc (5) architectur (4) power (4) awar (4)

Person: Norbert Wehn

DBLP: Wehn:Norbert

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1998

1994

1988

1987

Wrote 32 papers:

DATE-2015-BruggerVWTK #cpu #hybrid: Reverse longstaff-schwartz american option pricing on hybrid CPU/FPGA systems (CB, JAV, NW, ST, RK), pp. 1599–1602.
DATE-2015-Weis0ESVGKW #fault #metric #modelling: Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs (CW, MJ, PE, CS, PV, SG, MK, NW), pp. 495–500.
DATE-2014-0001GWKAWG #optimisation #performance #runtime: Exploiting expendable process-margins in DRAMs for run-time performance optimization (KC, SG, CW, MK, BA, NW, KG), pp. 1–6.
DATE-2014-LeupersWLRSFCJ #towards: Technology transfer towards Horizon 2020 (RL, NW, RL, MR, JS, LF, AC, BJ), p. 1.
DATE-2014-Sadri0WWB #3d #energy #optimisation #using: Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh (MS, MJ, CW, NW, LB), pp. 1–4.
DATE-2014-SchlichtmannKAEGGHNW #abstraction #design: Connecting different worlds — Technology abstraction for reliability-aware design and Test (US, VK, JAA, AE, CGD, MG, AH, SRN, NW), pp. 1–8.
DATE-2014-SchollW #hardware #implementation #set: Hardware implementation of a Reed-Solomon soft decoder based on information set decoding (SS, NW), pp. 1–6.
DAC-2013-0001WAWG #approach #empirical #estimation #towards: Towards variation-aware system-level power estimation of DRAMs: an empirical approach (KC, CW, BA, NW, KG), p. 8.
DAC-2013-HenkelBDGNSTW #lessons learnt #reliability #roadmap: Reliable on-chip systems in the nano-era: lessons learnt and future trends (JH, LB, ND, PG, SRN, MS, MBT, NW), p. 10.
DATE-2013-0001WAWG #3d #energy #modelling: System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs (KC, CW, BA, NW, KG), pp. 236–241.
DATE-2013-SchryverTW #monte carlo #multi: A multi-level Monte Carlo FPGA accelerator for option pricing in the Heston model (CdS, PT, NW), pp. 248–253.
DATE-2012-GomonyWAWG #mobile #realtime: DRAM selection and configuration for real-time mobile systems (MDG, CW, BA, NW, KG), pp. 51–56.
DATE-2012-WeisLBW #3d #energy #performance: An energy efficient DRAM subsystem for 3D integrated SoCs (CW, IL, LB, NW), pp. 1138–1141.
DATE-2011-WeisWLB #3d #design: Design space exploration for 3D-stacked DRAMs (CW, NW, IL, LB), pp. 389–394.
DATE-2010-MayIWR: A 150Mbit/s 3GPP LTE Turbo code decoder (MM, TI, NW, WR), pp. 1420–1425.
DATE-2010-MayWBZSHZT #agile #multi #prototype: A rapid prototyping system for error-resilient multi-processor systems-on-chip (MM, NW, AB, JZ, WS, AH, DZ, JT), pp. 375–380.
DATE-2009-0001BW #case study #fault #network: Error correction in single-hop wireless sensor networks — A case study (DS, MB, NW), pp. 1296–1301.
DATE-2009-0004SKAKW #novel: A novel LDPC decoder for DVB-S2 IP (SM, MS, MK, MA, FK, NW), pp. 1308–1313.
DATE-2008-MayAW #case study #design: A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder (MM, MA, NW), pp. 456–461.
DATE-2008-VogtW #configuration management #set: A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment (TV, NW), pp. 38–43.
DATE-2007-BrackALKWLRRF #complexity #generative #standard: Low complexity LDPC code decoders for next generation standards (TB, MA, TLE, FK, NW, NEL, FR, MR, LF), pp. 331–336.
DATE-2006-BrackKW #design: Disclosing the LDPC code decoder design space (TB, FK, NW), pp. 200–205.
DATE-2005-KienleBW: A Synthesizable IP Core for DVB-S2 LDPC Code Decoding (FK, TB, NW), pp. 100–105.
DATE-DF-2004-BerensKW #architecture #mobile: Channel Decoder Architecture for 3G Mobile Wireless Terminals (FB, GK, NW), pp. 192–197.
DATE-2003-GilbertTW #architecture #communication #embedded #multi: Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors (FG, MJT, NW), pp. 10356–10363.
DATE-2002-MichelWWM #hardware #trade-off: Hardware/Software Trade-Offs for Advanced 3G Channel Coding (HM, AW, NW, MM), pp. 396–401.
DATE-2001-WormLW #architecture #design #performance #power management: Design of low-power high-speed maximum a priori decoder architectures (AW, HL, NW), pp. 258–267.
DATE-2000-MunchWWMS #automation #power management: Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths (MM, NW, BW, RM, JS), pp. 624–631.
DATE-1998-WehnH #architecture #embedded #trade-off: Embedded DRAM Architectural Trade-Offs (NW, SH), pp. 704–708.
EDAC-1994-WurthW #logic #multi #optimisation #performance: Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization (BW, NW), pp. 630–634.
DAC-1988-WehnGCMR: A Defect-Tolerant and Fully Testable PLA (NW, MG, KC, PM, AR), pp. 22–33.
DAC-1987-SchuckWGK #compilation #design #experience #implementation: The ALGIC Silicon Compiler System: Implementation, Design Experience and Results (JS, NW, MG, GK), pp. 370–375.