Travelled to:1 × Germany
1 × USA
2 × France
Collaborated with:J.Abella F.J.Cazorla E.Quiñones F.Wartel E.Mezzetti M.Slijepcevic J.Jalle G.Farrall C.Curtsinger E.D.Berger Enrique Díaz Mikel Fernández C.Hernández A.Gogonel A.Baldovin Z.R.Stephenson B.Triquet C.Lo I.Broster L.Cucu-Grosjean T.Vardanega
Talks about:time (7) probabilist (4) cach (4) multicor (3) analysi (3) system (3) design (3) hardwar (2) complex (2) analys (2)
Person: Leonidas Kosmidis
DBLP: Kosmidis:Leonidas
Contributed to:
2015
201420142013
2017Wrote 7 papers:
- DATE-2015-WartelKGBSTQLMB #analysis #case study #hardware #platform
- Timing analysis of an avionics case study on complex hardware/software platforms (FW, LK, AG, AB, ZRS, BT, EQ, CL, EM, IB, JA, LCG, TV, FJC), pp. 397–402.
- DAC-2014-KosmidisQAFWC #certification #hardware
- Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware (LK, EQ, JA, GF, FW, FJC), p. 6.
- DAC-2014-SlijepcevicKAQC #manycore #realtime
- Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems (MS, LK, JA, EQ, FJC), p. 6.
- DATE-2014-JalleKAQC #design #manycore
- Bus designs for time-probabilistic multicore processors (JJ, LK, JA, EQ, FJC), pp. 1–6.
- DATE-2013-KosmidisAQC #design #realtime
- A cache design for probabilistically analysable real-time systems (LK, JA, EQ, FJC), pp. 513–518.
- DATE-2013-KosmidisCQABC #analysis #design #probability
- Probabilistic timing analysis on conventional cache designs (LK, CC, EQ, JA, EDB, FJC), pp. 603–606.
- AdaEurope-2017-DiazFKMHAC #analysis #bound #manycore #named #probability
- MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding (ED, MF, LK, EM, CH, JA, FJC), pp. 102–118.