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Travelled to:
1 × France
1 × India
1 × Spain
2 × Germany
5 × USA
Collaborated with:
O.S.Ünsal M.Valero S.Tomic T.Harris F.Zyulkyarov G.Yalcin O.Palomar E.Ayguadé J.A.Moreno J.Labarta D.Ortega J.Llosa T.Hayes V.Karakostas M.Nemirovsky C.E.Kulkarni M.Pericàs R.González D.A.Jiménez S.Stipic M.Duric A.Smith D.Burger V.Gajinov A.Sobe D.Harmanci A.Voronin J.Wamhoff P.Felber C.Fetzer
Talks about:
transact (6) memori (4) hardwar (3) effici (3) use (3) architectur (2) checkpoint (2) processor (2) system (2) energi (2)

Person: Adrián Cristal

DBLP DBLP: Cristal:Adri=aacute=n

Contributed to:

HPCA 20152015
PDP 20152015
DATE 20142014
PDP 20142014
DAC 20132013
DATE 20132013
DATE 20122012
ASPLOS 20102010
PPoPP 20102010
PPoPP 20092009
HPCA 20062006
HPCA 20042004

Wrote 13 papers:

HPCA-2015-HayesPUCV #algorithm #architecture #novel #sorting
VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors (TH, OP, OSÜ, AC, MV), pp. 26–38.
PDP-2015-MorenoULC #data flow #framework #named #performance #scalability
NanoCheckpoints: A Task-Based Asynchronous Dataflow Framework for Efficient and Scalable Checkpoint/Restart (JAM, OSÜ, JL, AC), pp. 99–102.
DATE-2014-DuricPSUCVB #execution #named #power management
EVX: Vector execution on low power EDGE cores (MD, OP, AS, OSÜ, AC, MV, DB), pp. 1–4.
PDP-2014-YalcinSHVWFUCF #detection #energy #fault #memory management #transaction
Combining Error Detection and Transactional Memory for Energy-Efficient Computing below Safe Operation Margins (GY, AS, DH, AV, JTW, PF, OSÜ, AC, CF), pp. 248–255.
DAC-2013-KarakostasTUNC #energy #performance
Improving the energy efficiency of hardware-assisted watchpoint systems (VK, ST, OSÜ, MN, AC), p. 6.
DATE-2013-YalcinUC #detection #fault #hardware #memory management #named #transaction #using
FaulTM: error detection and recovery using hardware transactional memory (GY, OSÜ, AC), pp. 220–225.
DATE-2012-StipicTZCUV #data access #hardware #metadata #named #performance
TagTM — accelerating STMs with hardware tags for fast meta-data access (SS, ST, FZ, AC, OSÜ, MV), pp. 39–44.
ASPLOS-2010-HarrisTCU #architecture #multi #runtime
Dynamic filtering: multi-purpose architecture support for language runtime systems (TH, ST, AC, OSÜ), pp. 39–52.
PPoPP-2010-ZyulkyarovHUCV #debugging #memory management #source code #transaction
Debugging programs that use atomic blocks and transactional memory (FZ, TH, OSÜ, AC, MV), pp. 57–66.
PPoPP-2009-KulkarniUCAV #how #transaction
Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions (CEK, OSÜ, AC, EA, MV), pp. 307–308.
PPoPP-2009-ZyulkyarovGUCAHV #game studies #interactive #memory management #multi #transaction #using
Atomic quake: using transactional memory in an interactive multiplayer game server (FZ, VG, OSÜ, AC, EA, TH, MV), pp. 25–34.
HPCA-2006-PericasCGJV
A decoupled KILO-instruction processor (MP, AC, RG, DAJ, MV), pp. 53–64.
HPCA-2004-CristalOLV #commit
Out-of-Order Commit Processors (AC, DO, JL, MV), pp. 48–59.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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