BibSLEIGH — Mateo

Travelled to:

1 × Canada
1 × India
1 × Mexico
1 × Spain
1 × United Kingdom
2 × France
2 × Germany
9 × USA

Collaborated with:

E.Ayguadé R.Espasa A.Cristal O.S.Ünsal J.Labarta J.Llosa B.Maric J.Abella A.Ramírez M.Peiron A.Pajuelo F.Zyulkyarov V.Subotic J.C.Sancho F.J.Cazorla O.Palomar T.Harris A.Falcón J.Corbal J.Larriba-Pey A.González J.González F.Quintana L.Villa P.Radojkovic V.Cakarevic J.Verdú M.Nemirovsky V.Marjanovic T.Ramírez O.J.Santana D.Ortega J.Zalamea J.Torres T.Hayes C.E.Kulkarni M.Pericàs R.González D.A.Jiménez D.A.Padua M.Jiménez V.Jiménez A.Buyuktosunoglu P.Bose F.P.O'Connell S.Stipic S.Tomic M.Duric A.Smith D.Burger V.Gajinov M.Moretó

Talks about:

vector (7) architectur (5) processor (5) transact (4) regist (4) code (4) multithread (3) perform (3) decoupl (3) thread (3)

Person: Mateo Valero

DBLP: Valero:Mateo

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2006

2004

2001

2000

1998

1997

1996

1995

1994

1993

Wrote 31 papers:

HPCA-2015-HayesPUCV #algorithm #architecture #novel #sorting: VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors (TH, OP, OSÜ, AC, MV), pp. 26–38.
HPCA-2015-JimenezBBOCV #manycore #performance: Increasing multicore system efficiency through intelligent bandwidth shifting (VJ, AB, PB, FPO, FJC, MV), pp. 39–50.
DATE-2014-DuricPSUCVB #execution #named #power management: EVX: Vector execution on low power EDGE cores (MD, OP, AS, OSÜ, AC, MV, DB), pp. 1–4.
DAC-2013-MaricAV #adaptation #energy #hybrid #named #predict #reliability: APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation (BM, JA, MV), p. 8.
DATE-2013-MaricAV #architecture #hybrid #performance #reliability #using: Efficient cache architectures for reliable hybrid voltage operation using EDC codes (BM, JA, MV), pp. 917–920.
PDP-2013-SuboticSLV #data flow #identification #modelling #programming: Identifying Critical Code Sections in Dataflow Programming Models (VS, JCS, JL, MV), pp. 29–37.
ASPLOS-2012-RadojkovicCMVPCNV #approach #parallel #statistics #thread: Optimal task assignment in multithreaded processors: a statistical approach (PR, VC, MM, JV, AP, FJC, MN, MV), pp. 235–248.
DATE-2012-StipicTZCUV #data access #hardware #metadata #named #performance: TagTM — accelerating STMs with hardware tags for fast meta-data access (SS, ST, FZ, AC, OSÜ, MV), pp. 39–44.
PDP-2011-SuboticSLV: The Impact of Application’s Micro-Imbalance on the Communication-Computation Overlap (VS, JCS, JL, MV), pp. 191–198.
PPoPP-2010-MarjanovicLAV #communication #effectiveness #hybrid: Effective communication and computation overlap with hybrid MPI/SMPSs (VM, JL, EA, MV), pp. 337–338.
PPoPP-2010-RadojkovicCVPCNV #concurrent #network #parallel #thread: Thread to strand binding of parallel network applications in massive multi-threaded systems (PR, VC, JV, AP, FJC, MN, MV), pp. 191–202.
PPoPP-2010-ZyulkyarovHUCV #debugging #memory management #source code #transaction: Debugging programs that use atomic blocks and transactional memory (FZ, TH, OSÜ, AC, MV), pp. 57–66.
PPoPP-2009-KulkarniUCAV #how #transaction: Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions (CEK, OSÜ, AC, EA, MV), pp. 307–308.
PPoPP-2009-ZyulkyarovGUCAHV #game studies #interactive #memory management #multi #transaction #using: Atomic quake: using transactional memory in an interactive multiplayer game server (FZ, VG, OSÜ, AC, EA, TH, MV), pp. 25–34.
HPCA-2008-RamirezPSV #performance #smt #thread: Runahead Threads to improve SMT performance (TR, AP, OJS, MV), pp. 149–158.
HPCA-2006-PericasCGJV: A decoupled KILO-instruction processor (MP, AC, RG, DAJ, MV), pp. 53–64.
HPCA-2004-CristalOLV #commit: Out-of-Order Commit Processors (AC, DO, JL, MV), pp. 48–59.
HPCA-2004-FalconRV #multi #thread: A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors (AF, AR, MV), pp. 244–253.
HPCA-2001-CorbalEV #generative: DLP + TLP Processors for the Next Generation of Media Workloads (JC, RE, MV), pp. 219–228.
HPCA-2000-RamirezLV: Trace Cache Redundancy: Red & Blue Traces (AR, JLLP, MV), pp. 325–333.
PLDI-2000-ZalameaLAV #code generation #pipes and filters: Improved spill code generation for software pipelined loops (JZ, JL, EA, MV), pp. 134–144.
HPCA-1998-GonzalezGV: Virtual-Physical Registers (AG, JG, MV), pp. 175–184.
PDP-1998-QuintanaEV #paradigm: A case for merging the ILP and DLP paradigms (FQ, RE, MV), pp. 217–224.
PDP-1998-VillaEV #architecture #effectiveness: Effective usage of vector registers in decoupled vector architectures (LV, RE, MV), pp. 495–501.
HPCA-1997-EspasaV #architecture #parallel #thread: Multithreaded Vector Architectures (RE, MV), pp. 237–248.
HPCA-1996-EspasaV #architecture: Decoupled Vector Architectures (RE, MV), pp. 281–290.
PDP-1996-TorresALV #framework #parallel: Loop Parallelization: Revisiting Framework of Unimodular Transformations (JT, EA, JL, MV), pp. 420–428.
HPCA-1995-LlosaVA: Non-Consistent Dual Register Files to Reduce Register Pressure (JL, MV, EA), pp. 22–31.
PDP-1995-EspasaVPJA #analysis: Quantitative analysis of vector code (RE, MV, DAP, MJ, EA), pp. 452–463.
PDP-1994-ValeroPA #multi: Access To Vectors In Multi-module Memories (MV, MP, EA), pp. 228–236.
PDP-1993-ValeroPA #multi: Access to streams in multiprocessor systems (MV, MP, EA), pp. 310–316.