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Travelled to:
1 × France
2 × USA
Collaborated with:
B.P.Ginsburg S.Park L.Peh M.Qazi T.S.Cho K.Lee J.Kong C.O.Chen T.Krishna S.Subramanian H.Hoffmann J.Holt G.Kurian E.Lau M.Maggio J.E.Miller S.M.Neuman M.E.Sinangil Y.Sinangil A.Agarwal S.Devadas
Talks about:
signal (2) self (2) low (2) no (2) reconfigur (1) processor (1) parallel (1) angstrom (1) optimum (1) nanotub (1)

Person: Anantha P. Chandrakasan

DBLP DBLP: Chandrakasan:Anantha_P=

Contributed to:

DATE 20132013
DAC 20122012
DAC 20082008

Wrote 5 papers:

DATE-2013-ChenPKSCP #configuration management #named
SMART: a single-cycle reconfigurable NoC for SoC applications (CHOC, SP, TK, SS, APC, LSP), pp. 338–343.
DATE-2013-ParkQPC #embedded #logic #self
40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS (SP, MQ, LSP, APC), pp. 1637–1642.
DAC-2012-HoffmannHKLMMNSSACD #self
Self-aware computing in the Angstrom processor (HH, JH, GK, EL, MM, JEM, SMN, MES, YS, AA, APC, SD), pp. 259–264.
DAC-2008-ChoLKC #design #power management
The design of a low power carbon nanotube chemical sensor system (TSC, KJL, JK, APC), pp. 84–89.
DAC-2008-GinsburgC #energy #parallel
The mixed signal optimum energy point: voltage and parallelism (BPG, APC), pp. 244–249.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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