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Travelled to:
1 × China
1 × Mexico
2 × Germany
3 × France
8 × USA
Collaborated with:
N.K.Jha W.J.Dally T.Krishna C.O.Chen W.Kwon S.Park K.Aisopos L.Shang A.P.Chandrakasan N.Agarwal H.Wang S.Malik J.Luo M.Qazi A.DeOrio V.Bertacco A.B.Kahng B.Li K.Samadi A.Kumar X.Chen G.Wei Y.Huang P.R.Prucnal S.Subramanian B.K.Daya A.Chandrakasan P.Juang H.Oki Y.Wang M.Martonosi D.Rubenstein
Talks about:
chip (6) network (5) no (5) system (3) explor (3) design (3) power (3) model (3) dynam (3) interconnect (2)

Person: Li-Shiuan Peh

DBLP DBLP: Peh:Li=Shiuan

Contributed to:

ASPLOS 20142014
DATE 20132013
HPCA 20132013
DAC 20122012
DAC 20112011
DATE 20092009
HPCA 20092009
DAC 20062006
DATE 20052005
HPCA 20052005
DATE 20032003
HPCA 20032003
ASPLOS 20022002
HPCA 20012001
HPCA 20002000

Wrote 17 papers:

ASPLOS-2014-KwonKP #multi
Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs (WCK, TK, LSP), pp. 715–728.
DATE-2013-ChenPKSCP #configuration management #named
SMART: a single-cycle reconfigurable NoC for SoC applications (CHOC, SP, TK, SS, APC, LSP), pp. 338–343.
DATE-2013-ParkQPC #embedded #logic #self
40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS (SP, MQ, LSP, APC), pp. 1637–1642.
HPCA-2013-KrishnaCKP #latency #using
Breaking the on-chip latency barrier using SMART (TK, CHOC, WCK, LSP), pp. 378–389.
DAC-2012-ParkKCDCP #prototype
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI (SP, TK, CHOC, BKD, AC, LSP), pp. 398–405.
DAC-2011-AisoposCP #fault #modelling
Enabling system-level modeling of variation-induced faults in networks-on-chips (KA, CHOC, LSP), pp. 930–935.
DAC-2011-DeOrioABP #architecture #distributed #manycore #named
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips (AD, KA, VB, LSP), pp. 912–917.
DATE-2009-KahngLPS #design #performance
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration (ABK, BL, LSP, KS), pp. 423–428.
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects (NA, LSP, NKJ), pp. 67–78.
DAC-2006-KumarSPJ #approach #coordination #named
HybDTM: a coordinated hardware-software approach for dynamic thermal management (AK, LS, LSP, NKJ), pp. 548–553.
DATE-2005-WangPM #energy #network
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks (HW, LSP, SM), pp. 1238–1243.
HPCA-2005-ChenPWHP #design #power management
Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems (XC, LSP, GYW, YKH, PRP), pp. 120–131.
DATE-2003-LuoPJ #communication #distributed #embedded #realtime #scalability
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems (JL, LSP, NKJ), pp. 11150–11151.
HPCA-2003-ShangPJ #network #optimisation #scalability
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks (LS, LSP, NKJ), pp. 91–102.
ASPLOS-2002-JuangOWMPR #case study #design #energy #experience #trade-off
Energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with ZebraNet (PJ, HO, YW, MM, LSP, DR), pp. 96–107.
HPCA-2001-PehD #architecture #pipes and filters
A Delay Model and Speculative Architecture for Pipelined Routers (LSP, WJD), pp. 255–266.
Flit-Reservation Flow Control (LSP, WJD), pp. 73–84.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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