Travelled to:1 × France
2 × Germany
2 × USA
Collaborated with:K.Skadron R.Zhang K.Wang M.R.Stan A.S.Hartman D.E.Thomas J.Caplan M.I.Mera P.Milder N.J.George B.H.Calhoun J.Lach K.Mazumdar
Talks about:system (2) execut (2) layer (2) cost (2) transient (1) processor (1) placement (1) signatur (1) deliveri (1) compress (1)
Person: Brett H. Meyer
DBLP: Meyer:Brett_H=
Contributed to:
20152014
201420112010Wrote 5 papers:
- DAC-2015-ZhangMMWSS #3d #design
- A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC (RZ, KM, BHM, KW, KS, MRS), p. 6.
- DAC-2014-WangMZSS
- Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization (KW, BHM, RZ, MRS, KS), p. 6.
- DATE-2014-CaplanMMM #execution #reliability #trade-off
- Trade-offs in execution signature compression for reliable processor systems (JC, MIM, PM, BHM), pp. 1–6.
- DATE-2011-MeyerGCLS #cost analysis #execution #safety #using
- Reducing the cost of redundant execution in safety-critical systems using relaxed dedication (BHM, NJG, BHC, JL, KS), pp. 1249–1254.
- DATE-2010-MeyerHT #effectiveness
- Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs (BHM, ASH, DET), pp. 1596–1601.