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Travelled to:
2 × France
2 × USA
Collaborated with:
K.Craig V.Chandra R.C.Aitken S.Nalam J.Boley M.Bhargava K.Mai B.H.Meyer N.J.George J.Lach K.Skadron Z.Qi J.Wang A.C.Cabe S.N.Wooters T.N.Blalock M.R.Stan
Talks about:
sram (4) system (3) design (3) write (2) dynam (2) heterogen (1) prototyp (1) nanoscal (1) deliveri (1) virtual (1)

Person: Benton H. Calhoun

DBLP DBLP: Calhoun:Benton_H=

Contributed to:

DAC 20132013
DATE 20132013
DATE 20112011
DAC 20102010

Wrote 6 papers:

DAC-2013-CalhounC #energy #flexibility #performance #power management
Flexible on-chip power delivery for energy efficient heterogeneous systems (BHC, KC), p. 6.
DATE-2013-BoleyCAC #analysis #estimation #performance
Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN (JB, VC, RCA, BHC), pp. 1819–1824.
DATE-2011-MeyerGCLS #cost analysis #execution #safety #using
Reducing the cost of redundant execution in safety-critical systems using relaxed dedication (BHM, NJG, BHC, JL, KS), pp. 1249–1254.
Dynamic write limited minimum operating voltage for nanoscale SRAMs (SN, VC, RCA, BHC), pp. 467–472.
DAC-2010-NalamBMC #design #optimisation #prototype
Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers (SN, MB, KM, BHC), pp. 138–143.
DAC-2010-QiWCWBCS #design
SRAM-based NBTI/PBTI sensor system design (ZQ, JW, ACC, SNW, TNB, BHC, MRS), pp. 849–852.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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