Travelled to:1 × Germany
3 × USA
Collaborated with:R.Panda M.Zhao Y.Fu D.Blaauw V.Zolotov S.Yan B.Cline K.Chopra A.Torres S.Pant B.Reschke T.Mewett S.Chandrasekaran
Talks about:decoupl (2) capacit (2) power (2) optim (2) chip (2) transistor (1) macromodel (1) placement (1) algorithm (1) stochast (1)
Person: Savithri Sundareswaran
DBLP: Sundareswaran:Savithri
Contributed to:
2008
200720062004Wrote 5 papers:
- DATE-2008-ClineCBTS #modelling
- Transistor-Specific Delay Modeling for SSTA (BC, KC, DB, AT, SS), pp. 592–597.
- DAC-2007-ZhaoPRFMCSY
- On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise (MZ, RP, BR, YF, TM, SC, SS, SY), pp. 162–167.
- DAC-2006-ZhaoPSYF #algorithm #linear #megamodelling #performance #programming #using
- A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming (MZ, RP, SS, SY, YF), pp. 217–222.
- DAC-2004-PantBZSP #analysis #approach #grid #power management #probability
- A stochastic approach To power grid analysis (SP, DB, VZ, SS, RP), pp. 171–176.
- DAC-2004-ZhaoFZSP #power management
- Optimal placement of power supply pads and pins (MZ, YF, VZ, SS, RP), pp. 165–170.