Travelled to:8 × USA
Collaborated with:D.Sylvester D.Blaauw S.R.Nassif ∅ V.Joshi J.Aarestad C.Lamech J.Plusquellic D.Acharyya B.Cline V.Sukharev A.Torres A.Srivastava S.Shah S.W.Director F.Liu S.B.K.Vrudhula
Talks about:variat (5) layout (3) die (3) interconnect (2) character (2) process (2) circuit (2) analysi (2) stress (2) metric (2)
Person: Kanak Agarwal
DBLP: Agarwal:Kanak
Contributed to:
20112010200820072006200520042003Wrote 10 papers:
- DAC-2011-AarestadLPAA #process
- Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect (JA, CL, JP, DA, KA), pp. 534–539.
- DAC-2010-Agarwal #composition
- Frequency domain decomposition of layouts for double dipole lithography (KA), pp. 404–407.
- DAC-2010-JoshiSTASB #modelling
- Closed-form modeling of layout-dependent mechanical stress (VJ, VS, AT, KA, DS, DB), pp. 673–678.
- DAC-2008-JoshiCSBA #power management #reduction #using
- Leakage power reduction using stress-enhanced layouts (VJ, BC, DS, DB, KA), pp. 912–917.
- DAC-2007-AgarwalN #process
- Characterizing Process Variation in Nanometer CMOS (KA, SRN), pp. 396–399.
- DAC-2006-AgarwalN #analysis #statistics
- Statistical analysis of SRAM cell stability (KA, SRN), pp. 57–62.
- DAC-2005-SrivastavaSASBD #correlation #estimation #parametricity #performance #power management
- Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance (AS, SS, KA, DS, DB, SWD), pp. 535–540.
- DAC-2004-AgarwalSBLNV #analysis #metric
- Variational delay metrics for interconnect timing analysis (KA, DS, DB, FL, SRN, SBKV), pp. 381–384.
- DAC-2003-AgarwalSB #effectiveness
- An effective capacitance based driver output model for on-chip RLC interconnects (KA, DS, DB), pp. 376–381.
- DAC-2003-AgarwalSB03a #metric
- Simple metrics for slew rate of RC circuits based on two circuit moments (KA, DS, DB), pp. 950–953.