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Travelled to:
1 × France
7 × USA
Collaborated with:
M.Aloqeely B.S.Carlson C.Y.Hou M.Z.Moricz U.Singh B.Halpin N.Sehgal M.K.Dhodhi I.Ahmad P.B.Berra A.Ghafoor T.D.C.Little
Talks about:
transistor (2) algorithm (2) synthesi (2) reorder (2) system (2) data (2) multiprocessor (1) multimedia (1) constraint (1) placement (1)

Person: C. Y. Roger Chen

DBLP DBLP: Chen:C=_Y=_Roger

Contributed to:

DAC 20012001
DAC 19941994
DAC 19931993
DAC 19921992
HPDC 19921992
DAC 19911991
DAC 19901990

Wrote 8 papers:

DAC-2001-HalpinCS #constraints #physics #using
Timing Driven Placement using Physical Net Constraints (BH, CYRC, NS), pp. 780–783.
DAC-1994-AloqeelyC #algorithm #synthesis
Sequencer-Based Data Path Synthesis of Regular Iterative Algorithms (MA, CYRC), pp. 155–160.
EDAC-1994-DhodhiAC #multi #synthesis
Synthesis of Application-Specific Multiprocessor Systems (MKD, IA, CYRC), p. 671.
DAC-1993-CarlsonC #order #performance
Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering (BSC, CYRC), pp. 361–366.
DAC-1992-HouC #algorithm #permutation
A Pin Permutation Algorithm for Improving Over-the-Cell Channel Routing (CYH, CYRC), pp. 594–599.
HPDC-1992-BerraCGL #data transformation #distributed #multi #network
Issues in Networking and Data Management of Distributed Multimedia Systems (PBB, CYRC, AG, TDCL), pp. 4–15.
DAC-1991-ChenM #pipes and filters #scheduling
Datapath Scheduling for Two-Level Pipelining (CYRC, MZM), pp. 603–606.
DAC-1990-SinghC #layout #matrix #order
A Transistor Reordering Technique for Gate Matrix Layout (US, CYRC), pp. 462–467.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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