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Travelled to:
1 × Germany
3 × USA
Collaborated with:
X.Li R.A.Rutenbar W.Yu C.Hu T.Chen M.Y.Ting F.Wang S.Sun C.Gu S.Saxena A.J.Strojwas Z.Wang Z.Yu R.Jiang J.Xiong
Talks about:
model (4) bayesian (3) variat (3) spatial (2) perform (2) extract (2) circuit (2) capacit (2) effici (2) scale (2)

Person: Wangyang Zhang

DBLP DBLP: Zhang:Wangyang

Contributed to:

DAC 20132013
DAC 20102010
DAC 20092009
DATE 20082008

Wrote 6 papers:

DAC-2013-WangZSLG #modelling #performance #reuse #scalability
Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data (FW, WZ, SS, XL, CG), p. 6.
DAC-2013-ZhangLSSR #automation #clustering
Automatic clustering of wafer spatial signatures (WZ, XL, SS, AJS, RAR), p. 6.
DAC-2010-ZhangCTL #modelling #multi #performance #scalability #towards
Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression (WZ, THC, MYT, XL), pp. 897–902.
Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference (WZ, XL, RAR), pp. 262–267.
Variational capacitance extraction of on-chip interconnects based on continuous surface model (WY, CH, WZ), pp. 758–763.
DATE-2008-ZhangYWYJX #correlation #performance #process #statistics
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation (WZ, WY, ZW, ZY, RJ, JX), pp. 580–585.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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