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Travelled to:
1 × Cyprus
1 × Germany
1 × Korea
2 × France
6 × USA
Collaborated with:
T.Kuo R.Liu P.Yuh Y.Chang J.Chen Y.Chen C.Li C.M.Wang P.Wang Y.Chang F.Lai G.Chen S.S.Sapatnekar K.King D.Shen S.Yu C.Chen P.Hsiu W.Hung Y.Chang A.P.Su M.Chuang K.Ho H.Li
Talks about:
cach (5) energi (3) base (3) architectur (2) algorithm (2) synthesi (2) schedul (2) biochip (2) memori (2) flash (2)

Person: Chia-Lin Yang

DBLP DBLP: Yang:Chia=Lin

Contributed to:

ASPLOS 20142014
DAC 20142014
DAC 20132013
DAC 20122012
DATE 20102010
DAC 20082008
DATE 20072007
SAC 20072007
DAC 20062006
DATE v1 20042004
SAC 20042004

Wrote 11 papers:

ASPLOS-2014-LiuSYYW #architecture #memory management #persistent
NVM duet: unified working memory and persistent store architecture (RSL, DYS, CLY, SCY, CYMW), pp. 455–470.
DAC-2014-LiuCYLHL #fault #locality #named
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs (RSL, MYC, CLY, CHL, KCH, HPL), p. 6.
DAC-2013-LiuYLC #named #using
DuraCache: a durable SSD cache using MLC NAND flash (RSL, CLY, CHL, GYC), p. 6.
DAC-2012-ChenHKYW #low cost
Age-based PCM wear leveling with nearly zero search cost (CHC, PCH, TWK, CLY, CYMW), pp. 453–458.
DATE-2010-ChenYW #memory management #named
PM-COSYN: PE and memory co-synthesis for MPSoCs (YJC, CLY, PHW), pp. 1590–1595.
DAC-2008-YuhSYC #algorithm
A progressive-ILP based routing algorithm for cross-referencing biochips (PHY, SSS, CLY, YWC), pp. 284–289.
DATE-2007-ChenKYK #energy #realtime #scheduling
Energy-efficient real-time task scheduling with task rejection (JJC, TWK, CLY, KJK), pp. 1629–1634.
SAC-2007-HungCYCS #algorithm #architecture #design #energy
An architectural co-synthesis algorithm for energy-aware network-on-chip design (WHH, YJC, CLY, YSC, APS), pp. 680–684.
DAC-2006-YuhYC #using
Placement of digital microfluidic biochips using the t-tree formulation (PHY, CLY, YWC), pp. 931–934.
DATE-v1-2004-ChangYL
Value-Conscious Cache: Simple Technique for Reducing Cache Access Power (YJC, CLY, FL), pp. 16–21.
SAC-2004-ChenKY #constraints #energy #scheduling
Profit-driven uniprocessor scheduling with energy and timing constraints (JJC, TWK, CLY), pp. 834–840.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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