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Travelled to:
1 × Germany
3 × USA
Collaborated with:
C.Visweswariah N.Venkateswaran J.Xiong V.Zolotov A.Mallik P.Banerjee H.Zhou V.Kuruvilla J.Piaget N.Chandrachoodan P.Feldmann S.Abbaspour G.Schaeffer R.Banerji H.Gupta J.G.Hemmett E.A.Foreman J.Leitzen
Talks about:
time (4) statist (3) analysi (3) driver (2) comput (2) optim (2) min (2) max (2) determinist (1) threshold (1)

Person: Debjit Sinha

DBLP DBLP: Sinha:Debjit

Contributed to:

DAC 20132013
DAC 20122012
DAC 20082008
DATE 20062006

Wrote 5 papers:

DAC-2013-KuruvillaSPVC #analysis #optimisation #set #statistics
Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization (VK, DS, JP, CV, NC), p. 7.
DAC-2012-SinhaVVXZ #concept #statistics
Reversible statistical max/min operation: concept and applications to timing (DS, CV, NV, JX, VZ), pp. 1067–1073.
DAC-2012-ZolotovSHFVXLV #analysis #statistics
Timing analysis with nonseparable statistical and deterministic variations (VZ, DS, JGH, EAF, CV, JX, JL, NV), pp. 1061–1066.
DAC-2008-FeldmannASSBG #analysis #modelling #multi
Driver waveform computation for timing analysis with multiple voltage threshold driver models (PF, SA, DS, GS, RB, HG), pp. 425–428.
DATE-2006-MallikSBZ #design #optimisation #power management
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment (AM, DS, PB, HZ), pp. 618–623.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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