Travelled to:4 × USA
Collaborated with:R.E.Bryant C.H.Seger M.Pandey R.Raimi K.S.Brace K.Cho T.J.Sheffler
Talks about:formal (3) use (3) trajectori (2) circuit (2) symbol (2) verif (2) simul (2) evalu (2) microprocessor (1) methodolog (1)
Person: Derek L. Beatty
DBLP: Beatty:Derek_L=
Contributed to:
19961994199119881987Wrote 5 papers:
- DAC-1996-PandeyRBB #array #evaluation #using #verification
- Formal Verification of PowerPC Arrays Using Symbolic Trajectory Evaluation (MP, RR, DLB, REB), pp. 649–654.
- DAC-1994-BeattyB #simulation #using #verification
- Formally Verifying a Microprocessor Using a Simulation Methodology (DLB, REB), pp. 596–602.
- DAC-1991-BryantBS #evaluation #hardware #verification
- Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation (REB, DLB, CJHS), pp. 397–402.
- DAC-1988-BeattyB #analysis #incremental #performance #using
- Fast Incremental Circuit Analysis Using Extracted Hierarchy (DLB, REB), pp. 495–500.
- DAC-1987-BryantBBCS #named
- COSMOS: A Compiled Simulator for MOS Circuits (REB, DLB, KSB, KC, TJS), pp. 9–16.