Travelled to:
11 × USA
3 × Germany
5 × France
Collaborated with:
R.L.Lysecky T.Givargis A.Gordon-Ross C.Zhang D.Gajski G.Stitt S.Sirowy C.Huang S.Lonardi B.Miller S.Cotterell S.Narayan Y.Wu ∅ P.Viana W.A.Najjar E.Barros D.Sheldon S.X.Tan N.Dutt J.Yang J.Henkel E.Hwang Y.Hsu R.Mannion H.Hsieh J.Gong E.J.Keogh D.C.Suresh J.R.Villarreal
Talks about:
system (10) partit (9) cach (8) softwar (5) dynam (5) fpga (5) use (5) configur (4) hardwar (4) design (4)
Person: Frank Vahid
DBLP: Vahid:Frank
Contributed to:
Wrote 30 papers:
- DAC-2013-MillerVG #modelling #physics #statistics #using
- Exploration with upgradeable models using statistical methods for physical model emulation (BM, FV, TG), p. 6.
- DATE-2012-MillerVG #automation #cyber-physical #mockup #named #testing #using
- MEDS: Mockup Electronic Data Sheets for automated testing of cyber-physical systems using digital mockups (BM, FV, TG), pp. 1417–1420.
- DAC-2010-SirowyHV #online
- Online SystemC emulation acceleration (SS, CH, FV), pp. 30–35.
- DAC-2009-HuangV
- Transmuting coprocessors: dynamic loading of FPGA coprocessors (CH, FV), pp. 848–851.
- DAC-2007-Gordon-RossV #configuration management #self
- A Self-Tuning Configurable Cache (AGR, FV), pp. 234–237.
- DATE-2007-Gordon-RossVVNB #configuration management #energy #performance
- A one-shot configurable-cache tuner for improved energy and performance (AGR, PV, FV, WAN, EB), pp. 755–760.
- DATE-2007-SheldonVL #design #interactive #paradigm #using
- Interactive presentation: Soft-core processor customization using the design of experiments paradigm (DS, FV, SL), pp. 821–826.
- DATE-2007-SirowyWLV #clustering
- Two-level microprocessor-accelerator partitioning (SS, YW, SL, FV), pp. 313–318.
- DATE-2007-SirowyWLV07a #multi
- Clock-frequency assignment for multiple clock domain systems-on-a-chip (SS, YW, SL, FV), pp. 397–402.
- DAC-2006-VianaGKBV #configuration management #performance
- Configurable cache subsetting for fast cache tuning (PV, AGR, EJK, EB, FV), pp. 695–700.
- DATE-2005-LyseckyV #case study #clustering #hardware #using
- A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning (RLL, FV), pp. 18–23.
- DATE-2005-MannionHCV #network #programmable #synthesis
- System Synthesis for Networks of Programmable Blocks (RM, HH, SC, FV), pp. 888–893.
- DATE-2005-StittV #approach #clustering #decompiler
- A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms (GS, FV), pp. 396–397.
- DAC-2004-LyseckyVT #compilation
- Dynamic FPGA routing for just-in-time FPGA compilation (RLL, FV, SXDT), pp. 954–959.
- DATE-v1-2004-Gordon-RossVD #automation #embedded
- Automatic Tuning of Two-Level Caches to Embedded Applications (AGR, FV, ND), pp. 208–213.
- DATE-v1-2004-LyseckyV #architecture #clustering #configuration management #hardware #logic
- A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning (RLL, FV), pp. 480–485.
- DATE-v1-2004-ZhangV #memory management #using
- Using a Victim Buffer in an Application-Specific Memory Hierarchy (CZ, FV), pp. 220–227.
- DATE-v1-2004-ZhangVL #architecture #embedded #self
- A Self-Tuning Cache Architecture for Embedded Systems (CZ, FV, RLL), pp. 142–147.
- DATE-v1-2004-ZhangYV
- Low Static-Power Frequent-Value Data Caches (CZ, JY, FV), pp. 214–219.
- DAC-2003-LyseckyV #logic
- On-chip logic minimization (RLL, FV), pp. 334–337.
- DAC-2003-StittLV #approach #clustering #hardware
- Dynamic hardware/software partitioning: a first approach (GS, RLL, FV), pp. 250–255.
- LCTES-2003-SureshNVVS #clustering #embedded #hardware #profiling #tool support
- Profiling tools for hardware/software partitioning of embedded applications (DCS, WAN, FV, JRV, GS), pp. 189–198.
- DAC-2002-LyseckyCV #memory management #performance #profiling
- A fast on-chip profiler memory (RLL, SC, FV), pp. 28–33.
- DATE-2000-HenkeGV #design #estimation #performance
- Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design (JH, TG, FV), pp. 333–338.
- DATE-2000-LyseckyVG #latency
- Techniques for Reducing Read Latency of Core Bus Wrappers (RLL, FV, TG), pp. 84–91.
- DATE-1999-HwangVH #clustering #functional #power management
- FSMD Functional Partitioning for Low Power (EH, FV, YCH), pp. 22–27.
- DAC-1998-GajskiVNG
- System-level exploration with SpecSyn (DG, FV, SN, JG), pp. 812–817.
- EDTC-1997-Vahid #clustering #functional
- Procedure cloning: a transformation for improved system-level functional partitioning (FV), pp. 487–492.
- EDAC-1994-GajskiVN #refinement
- A System-Design Methodology: Executable-Specification Refinement (DG, FV, SN), pp. 458–463.
- DAC-1992-VahidG #clustering #design #specification
- Specification Partitioning for System Design (FV, DG), pp. 219–224.