BibSLEIGH corpus
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Travelled to:
3 × USA
Collaborated with:
D.Hebert D.Lacy N.Phillips J.Tellier M.Kearney T.Elkind R.Beaven
Talks about:
simul (4) concurr (2) speed (2) digit (2) base (2) methodolog (1) techniqu (1) suppress (1) structur (1) accuraci (1)

Person: Ernst Ulrich

DBLP DBLP: Ulrich:Ernst

Contributed to:

DAC 19831983
DAC 19821982
DAC 19801980

Wrote 4 papers:

DAC-1983-Ulrich #concurrent #design #simulation #verification
A design verification methodology based on concurrent simulation and clock suppression (EU), pp. 709–712.
DAC-1982-UlrichH #modelling #network #simulation
Speed and accuracy in digital network simulation based on structural modeling (EU, DH), pp. 587–593.
DAC-1980-Ulrich #flexibility #logic #performance #simulation
Table lookup techniques for fast and flexible digital logic simulation (EU), pp. 560–563.
DAC-1980-UlrichLPTKEB #concurrent #fault #performance #simulation
High-speed concurrent fault simulation with vectors and scalars (EU, DL, NP, JT, MK, TE, RB), pp. 374–380.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.