BibSLEIGH — Guang_R

Travelled to:

1 × Germany
1 × Italy
1 × Portugal
1 × Sweden
1 × The Netherlands
14 × USA
2 × Canada

Collaborated with:

R.Govindarajan V.C.Sreedhar A.Douillet E.R.Altman Q.Ning H.Rong D.M.Tullsen D.E.Vengroff J.Wang A.Stoutchinin S.Lelait C.Eisenbeis Y.Lee K.B.Theobald H.H.J.Hum Y.Wong H.Wei J.Yu H.Yu C.Zhang S.Ryan J.C.Ruttenberg W.Lichtenstein L.J.Hendren C.Mukerji S.Shrestha J.Manzano A.Márquez J.Feo G.Tan D.Fan J.Zhang A.Russo Y.Zhang W.Zhu V.Sarkar Z.Tang A.Sodan O.Maquelin J.Schultz X.Tian J.N.Amaral J.C.Dehnert S.Jain

Talks about:

pipelin (11) softwar (10) loop (6) optim (5) alloc (5) schedul (4) regist (4) architectur (3) framework (3) dimension (3)

Person: Guang R. Gao

DBLP: Gao:Guang_R=

Contributed to:

2015

2010

2008

2007

2005

2004

2001

1999

1998

1997

1996

1995

1993

1992

1991

Wrote 23 papers:

CGO-2015-ShresthaGMMF #concurrent #locality: Locality aware concurrent start for stencil applications (SS, GRG, JM, AM, JF), pp. 157–166.
CGO-2010-WeiYYG #communication #pipes and filters #source code: Minimizing communication in rate-optimal software pipelining for stream programs (HW, JY, HY, GRG), pp. 210–217.
PPoPP-2008-TanFZRG #architecture #experience #manycore #memory management #optimisation: Experience on optimizing irregular computation for memory hierarchy in manycore architecture (GT, DF, JZ, AR, GRG), pp. 279–280.
PPoPP-2007-ZhangSZSG #concurrent: Optimized lock assignment and allocation: a method for exploiting concurrency among critical sections (YZ, VCS, WZ, VS, GRG), pp. 146–147.
PLDI-2005-RongDG #multi #pipes and filters: Register allocation for software pipelined multi-dimensional loops (HR, AD, GRG), pp. 154–167.
CGO-2004-RongDGG #code generation #multi #pipes and filters: Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops (HR, AD, RG, GRG), pp. 175–188.
CGO-2004-RongTGDG #multi #pipes and filters: Single-Dimension Software Pipelining for Multi-Dimensional Loops (HR, ZT, RG, AD, GRG), pp. 163–174.
CC-2001-StoutchininAGDJD #induction #pointer: Speculative Prefetching of Induction Pointers (AS, JNA, GRG, JCD, SJ, AD), pp. 289–303.
CC-1999-ZhangGRG #performance #pipes and filters: Efficient State-Diagram Construction Methods for Software Pipelining (CZ, RG, SR, GRG), pp. 153–167.
HPCA-1999-TullsenG #architecture #compilation #execution #parallel #thread: Multithreaded Execution Architecture and Compilation (DMT, GRG), p. 321.
CC-1998-LelaitGE #algorithm #performance: A New Fast Algorithm for Optimal Register Allocation in Modulo Scheduled Loops (SL, GRG, CE), pp. 204–218.
HPCA-1998-VengroffG #branch #estimation #performance #predict #re-engineering: Partial Sampling with Reverse State Reconstruction: A New Technique for Branch Predictor Performance Estimation (DEV, GRG), pp. 342–351.
PPoPP-1997-SodanGMST #architecture #case study #experience #parallel #thread: Experiences with Non-numeric Applications on Multithreaded Architectures (AS, GRG, OM, JUS, XT), pp. 124–135.
CC-1996-WangG #named #pipes and filters: Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops (JW, GRG), pp. 1–17.
HPCA-1996-GovindarajanAG #hardware #pipes and filters: Co-Scheduling Hardware and Software Pipelines (RG, ERA, GRG), pp. 52–61.
PLDI-1996-RuttenbergGLS #compilation #heuristic #pipes and filters: Software Pipelining Showdown: Optimal vs. Heuristic Methods in a Production Compiler (JCR, GRG, WL, AS), pp. 1–11.
PLDI-1996-SreedharGL #analysis #data flow #framework #graph #incremental #using: A New Framework for Exhaustive and Incremental Data Flow Analysis Using DJ Graphs (VCS, GRG, YFL), pp. 278–290.
HPCA-1995-TheobaldHG #design #hybrid: A Design Frame for Hybrid Access Caches (KBT, HHJH, GRG), pp. 144–153.
PLDI-1995-AltmanGG #pipes and filters #scheduling: Scheduling and Mapping: Software Pipelining in the Presence of Structural Hazards (ERA, RG, GRG), pp. 139–150.
POPL-1995-SreedharG #algorithm #linear: A Linear Time Algorithm for Placing phi-nodes (VCS, GRG), pp. 62–73.
POPL-1993-NingG #framework #novel #pipes and filters: A Novel Framework of Register Allocation for Software Pipelining (QN, GRG), pp. 29–42.
CC-1992-HendrenGAM #framework #graph: A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs (LJH, GRG, ERA, CM), pp. 176–191.
PLDI-1991-GaoWN #petri net #scheduling: A Timed Petri-Net Model for Fine-Grain Loop Scheduling (GRG, YBW, QN), pp. 204–218.